| Message ID | 20220217123223.748184-1-tejaskumarx.surendrakumar.upadhyay@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gt: use get_reset_domain() helper | expand |
On Thu, Feb 17, 2022 at 06:02:23PM +0530, Tejas Upadhyay wrote: > We dont need to implement reset_domain in intel_engine > _setup(), but can be done as a helper. Implemented as > engine->reset_domain = get_reset_domain(). > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> it is a good non-functional clean-up in the engine setup function and we will need this soon to be called from more other places, so: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 74 +++++++++++++---------- > 1 file changed, 42 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index e53008b4dd05..e855c801ba28 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -293,6 +293,46 @@ static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) > GEM_DEBUG_WARN_ON(iir); > } > > +static u32 get_reset_domain(u8 ver, enum intel_engine_id id) > +{ > + u32 reset_domain; > + > + if (ver >= 11) { > + static const u32 engine_reset_domains[] = { > + [RCS0] = GEN11_GRDOM_RENDER, > + [BCS0] = GEN11_GRDOM_BLT, > + [VCS0] = GEN11_GRDOM_MEDIA, > + [VCS1] = GEN11_GRDOM_MEDIA2, > + [VCS2] = GEN11_GRDOM_MEDIA3, > + [VCS3] = GEN11_GRDOM_MEDIA4, > + [VCS4] = GEN11_GRDOM_MEDIA5, > + [VCS5] = GEN11_GRDOM_MEDIA6, > + [VCS6] = GEN11_GRDOM_MEDIA7, > + [VCS7] = GEN11_GRDOM_MEDIA8, > + [VECS0] = GEN11_GRDOM_VECS, > + [VECS1] = GEN11_GRDOM_VECS2, > + [VECS2] = GEN11_GRDOM_VECS3, > + [VECS3] = GEN11_GRDOM_VECS4, > + }; > + GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || > + !engine_reset_domains[id]); > + reset_domain = engine_reset_domains[id]; > + } else { > + static const u32 engine_reset_domains[] = { > + [RCS0] = GEN6_GRDOM_RENDER, > + [BCS0] = GEN6_GRDOM_BLT, > + [VCS0] = GEN6_GRDOM_MEDIA, > + [VCS1] = GEN8_GRDOM_MEDIA2, > + [VECS0] = GEN6_GRDOM_VECS, > + }; > + GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || > + !engine_reset_domains[id]); > + reset_domain = engine_reset_domains[id]; > + } > + > + return reset_domain; > +} > + > static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, > u8 logical_instance) > { > @@ -328,38 +368,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, > engine->id = id; > engine->legacy_idx = INVALID_ENGINE; > engine->mask = BIT(id); > - if (GRAPHICS_VER(gt->i915) >= 11) { > - static const u32 engine_reset_domains[] = { > - [RCS0] = GEN11_GRDOM_RENDER, > - [BCS0] = GEN11_GRDOM_BLT, > - [VCS0] = GEN11_GRDOM_MEDIA, > - [VCS1] = GEN11_GRDOM_MEDIA2, > - [VCS2] = GEN11_GRDOM_MEDIA3, > - [VCS3] = GEN11_GRDOM_MEDIA4, > - [VCS4] = GEN11_GRDOM_MEDIA5, > - [VCS5] = GEN11_GRDOM_MEDIA6, > - [VCS6] = GEN11_GRDOM_MEDIA7, > - [VCS7] = GEN11_GRDOM_MEDIA8, > - [VECS0] = GEN11_GRDOM_VECS, > - [VECS1] = GEN11_GRDOM_VECS2, > - [VECS2] = GEN11_GRDOM_VECS3, > - [VECS3] = GEN11_GRDOM_VECS4, > - }; > - GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || > - !engine_reset_domains[id]); > - engine->reset_domain = engine_reset_domains[id]; > - } else { > - static const u32 engine_reset_domains[] = { > - [RCS0] = GEN6_GRDOM_RENDER, > - [BCS0] = GEN6_GRDOM_BLT, > - [VCS0] = GEN6_GRDOM_MEDIA, > - [VCS1] = GEN8_GRDOM_MEDIA2, > - [VECS0] = GEN6_GRDOM_VECS, > - }; > - GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || > - !engine_reset_domains[id]); > - engine->reset_domain = engine_reset_domains[id]; > - } > + engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915), > + id); > engine->i915 = i915; > engine->gt = gt; > engine->uncore = gt->uncore; > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e53008b4dd05..e855c801ba28 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -293,6 +293,46 @@ static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir) GEM_DEBUG_WARN_ON(iir); } +static u32 get_reset_domain(u8 ver, enum intel_engine_id id) +{ + u32 reset_domain; + + if (ver >= 11) { + static const u32 engine_reset_domains[] = { + [RCS0] = GEN11_GRDOM_RENDER, + [BCS0] = GEN11_GRDOM_BLT, + [VCS0] = GEN11_GRDOM_MEDIA, + [VCS1] = GEN11_GRDOM_MEDIA2, + [VCS2] = GEN11_GRDOM_MEDIA3, + [VCS3] = GEN11_GRDOM_MEDIA4, + [VCS4] = GEN11_GRDOM_MEDIA5, + [VCS5] = GEN11_GRDOM_MEDIA6, + [VCS6] = GEN11_GRDOM_MEDIA7, + [VCS7] = GEN11_GRDOM_MEDIA8, + [VECS0] = GEN11_GRDOM_VECS, + [VECS1] = GEN11_GRDOM_VECS2, + [VECS2] = GEN11_GRDOM_VECS3, + [VECS3] = GEN11_GRDOM_VECS4, + }; + GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || + !engine_reset_domains[id]); + reset_domain = engine_reset_domains[id]; + } else { + static const u32 engine_reset_domains[] = { + [RCS0] = GEN6_GRDOM_RENDER, + [BCS0] = GEN6_GRDOM_BLT, + [VCS0] = GEN6_GRDOM_MEDIA, + [VCS1] = GEN8_GRDOM_MEDIA2, + [VECS0] = GEN6_GRDOM_VECS, + }; + GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || + !engine_reset_domains[id]); + reset_domain = engine_reset_domains[id]; + } + + return reset_domain; +} + static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, u8 logical_instance) { @@ -328,38 +368,8 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, engine->id = id; engine->legacy_idx = INVALID_ENGINE; engine->mask = BIT(id); - if (GRAPHICS_VER(gt->i915) >= 11) { - static const u32 engine_reset_domains[] = { - [RCS0] = GEN11_GRDOM_RENDER, - [BCS0] = GEN11_GRDOM_BLT, - [VCS0] = GEN11_GRDOM_MEDIA, - [VCS1] = GEN11_GRDOM_MEDIA2, - [VCS2] = GEN11_GRDOM_MEDIA3, - [VCS3] = GEN11_GRDOM_MEDIA4, - [VCS4] = GEN11_GRDOM_MEDIA5, - [VCS5] = GEN11_GRDOM_MEDIA6, - [VCS6] = GEN11_GRDOM_MEDIA7, - [VCS7] = GEN11_GRDOM_MEDIA8, - [VECS0] = GEN11_GRDOM_VECS, - [VECS1] = GEN11_GRDOM_VECS2, - [VECS2] = GEN11_GRDOM_VECS3, - [VECS3] = GEN11_GRDOM_VECS4, - }; - GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || - !engine_reset_domains[id]); - engine->reset_domain = engine_reset_domains[id]; - } else { - static const u32 engine_reset_domains[] = { - [RCS0] = GEN6_GRDOM_RENDER, - [BCS0] = GEN6_GRDOM_BLT, - [VCS0] = GEN6_GRDOM_MEDIA, - [VCS1] = GEN8_GRDOM_MEDIA2, - [VECS0] = GEN6_GRDOM_VECS, - }; - GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) || - !engine_reset_domains[id]); - engine->reset_domain = engine_reset_domains[id]; - } + engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915), + id); engine->i915 = i915; engine->gt = gt; engine->uncore = gt->uncore;
We dont need to implement reset_domain in intel_engine _setup(), but can be done as a helper. Implemented as engine->reset_domain = get_reset_domain(). Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 74 +++++++++++++---------- 1 file changed, 42 insertions(+), 32 deletions(-)