From patchwork Wed Feb 23 05:58:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12756454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51D65C433EF for ; Wed, 23 Feb 2022 05:59:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5448B10E9DE; Wed, 23 Feb 2022 05:59:09 +0000 (UTC) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5542010E966; Wed, 23 Feb 2022 05:59:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645595945; x=1677131945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AD5IB1Lfku9eRUR3ytYZ4pov3SYDjYyCciBQj20OH0o=; b=BlogS+2TQZmZaZChSQKRkRtt9kopL2hwqrrJug3QxXs/llHMsHbPTc1f JLgMOarf8+aopr/ok8qPWAhhrd0JrH5ppZLCzJc8sPLQEys+DCR0Jh+mJ r8yUTpn/7cLuzpXFE14CJ3TBHzEKf2BPKHmQ7caNCRkpOoe9SJPcUffNQ D02FN+njApOEedKLF+8SH8Zc5HEa77halGTuzwUNVCtXvDYniTm1YPmko j2r4DVEcwQdnua6d6IvEdfmZK0Q/sPkzw7nEtusgWxBYYpzwqAbTdzEPT fmtmSwv3Lfx8zzK73q7sAfN1TDYzEGf3AMBOpmCsU2oa+jAAgRWCjhEix Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10266"; a="312606225" X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="312606225" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2022 21:59:04 -0800 X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="706908152" Received: from shreyasj-mobl1.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.93.217]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2022 21:59:04 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Feb 2022 21:58:55 -0800 Message-Id: <20220223055900.415627-2-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220223055900.415627-1-michael.cheng@intel.com> References: <20220223055900.415627-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v11 1/6] drm: Add arch arm64 for drm_clflush_virt_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc performs a flush by first performing a clean, follow by an invalidation operation. v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion. v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h Signed-off-by: Michael Cheng Reviewed-by: Matt Roper Reported-by: kernel test robot Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/gpu/drm/drm_cache.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..f7b17e0d57f0 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -28,6 +28,7 @@ * Authors: Thomas Hellström */ +#include #include #include #include @@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); + #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif