From patchwork Mon Mar 21 22:38:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12787808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9563C433EF for ; Mon, 21 Mar 2022 22:38:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 621E110E05D; Mon, 21 Mar 2022 22:38:25 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id A6EC010E05D; Mon, 21 Mar 2022 22:38:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1647902304; x=1679438304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7YL+lrwrPUIiZqdbOjoLXeDjhjKaMrv7OeYOpwYJ6No=; b=PxDoTp4skPn+vU6lgmh5gLOIfZgCqoc+GnVqvsBIV/4LH5j/Zxxs6ODn X9RoKAAtqNcmf2qfjYBLP22gFRTdvz7ELhObvt+DvxSiUR8NBCnRzrjnI dyeiqguI59Z8zFLXZg4hWKgtS+qQHOpZg9ChYy+qLecyr05/rWUeCvvmD aNFWhDDtRFyUHeTJfAHEvTd705Zm+mXFmGsB9L61HB281ZXAv/QsCtQ0a IwbYoO3QwEhxDESm2J5AW27JShelg8GI2FPHXnucHiCPBIlh8ar/ulksj Yt+36nxz/e5o6Ci/pkm+ZjVyswHEKoRUKwkf7rmkSa1MTCflOnU36LDgC w==; X-IronPort-AV: E=McAfee;i="6200,9189,10293"; a="255227164" X-IronPort-AV: E=Sophos;i="5.90,199,1643702400"; d="scan'208";a="255227164" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2022 15:38:24 -0700 X-IronPort-AV: E=Sophos;i="5.90,199,1643702400"; d="scan'208";a="518616763" Received: from prithika-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.251.16.248]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2022 15:38:23 -0700 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Mon, 21 Mar 2022 15:38:16 -0700 Message-Id: <20220321223819.72833-3-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220321223819.72833-1-michael.cheng@intel.com> References: <20220321223819.72833-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v13 2/5] drm/i915/gt: Drop invalidate_csb_entries X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Drop invalidate_csb_entries and directly call drm_clflush_virt_range. This allows for one less function call, and prevent complier errors when building for non-x86 architectures. v2(Michael Cheng): Drop invalidate_csb_entries function and directly invoke drm_clflush_virt_range. Thanks to Tvrtko for the sugguestion. v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range. Thanks to Tvrtko for pointing this out. v4(Michael Cheng): Simplify &execlists->csb_status[0] to execlists->csb_status. Thanks to Matt Roper for the suggestion. Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- .../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index e1470bb60f34..5f8cf4942f07 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1651,12 +1651,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists, return inactive; } -static void invalidate_csb_entries(const u64 *first, const u64 *last) -{ - clflush((void *)first); - clflush((void *)last); -} - /* * Starting with Gen12, the status has a new format: * @@ -2004,7 +1998,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) * the wash as hardware, working or not, will need to do the * invalidation before. */ - invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); + drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0])); /* * We assume that any event reflects a change in context flow @@ -2788,8 +2782,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine) /* Check that the GPU does indeed update the CSB entries! */ memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64)); - invalidate_csb_entries(&execlists->csb_status[0], - &execlists->csb_status[reset_value]); + drm_clflush_virt_range(execlists->csb_status, + execlists->csb_size * + sizeof(execlists->csb_status)); /* Once more for luck and our trusty paranoia */ ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,