diff mbox series

[i-g-t,2/2] tests/gem_ctx_engines: handle missing set_caching

Message ID 20220401110902.446305-2-matthew.auld@intel.com (mailing list archive)
State New, archived
Headers show
Series [i-g-t,1/2] tests/kms_pwrite_crc: handle missing get_caching | expand

Commit Message

Matthew Auld April 1, 2022, 11:09 a.m. UTC 
Not supported on discrete. Here the object will already have the GTT
caching bits enabled, and the mapping will be WB, which looks inline
with what the test is expecting here.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4926
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Nirmoy Das <nirmoy.das@linux.intel.com>
---
 tests/i915/gem_ctx_engines.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/tests/i915/gem_ctx_engines.c b/tests/i915/gem_ctx_engines.c
index de4b822c..19cf9b05 100644
--- a/tests/i915/gem_ctx_engines.c
+++ b/tests/i915/gem_ctx_engines.c
@@ -492,7 +492,8 @@  static void independent(int i915, const intel_ctx_t *base_ctx,
 	param.ctx_id = gem_context_create(i915);
 	gem_context_set_param(i915, &param);
 
-	gem_set_caching(i915, results.handle, I915_CACHING_CACHED);
+	if (!gem_has_lmem(i915))
+		gem_set_caching(i915, results.handle, I915_CACHING_CACHED);
 	map = gem_mmap__cpu(i915, results.handle, 0, 4096, PROT_READ);
 	gem_set_domain(i915, results.handle,
 		       I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);