| Message ID | 20220413152852.7336-2-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915/fbc: Consult hw.crtc instead of uapi.crtc | expand |
On Wed, Apr 13, 2022 at 06:28:52PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > intel_fbc_check_plane() is supposed to an int, not a boolean. > So replace the bogus 'return false's with the correct 'return 0's. > These were accidental copy-paste mistakes when the code got moved > into intel_fbc_check_plane() from somewhere else tht did return > a boolean. > > No functional issue here since false==0. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Good catch Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index ff303c7d3a57..966970d1cf0a 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1086,7 +1086,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > */ > if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) { > plane_state->no_fbc_reason = "PSR2 enabled"; > - return false; > + return 0; > } > > if (!pixel_format_is_valid(plane_state)) { > @@ -1112,7 +1112,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && > fb->format->has_alpha) { > plane_state->no_fbc_reason = "per-pixel alpha not supported"; > - return false; > + return 0; > } > > if (!intel_fbc_hw_tracking_covers_screen(plane_state)) { > @@ -1128,7 +1128,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > if (DISPLAY_VER(i915) >= 9 && > plane_state->view.color_plane[0].y & 3) { > plane_state->no_fbc_reason = "plane start Y offset misaligned"; > - return false; > + return 0; > } > > /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ > @@ -1136,7 +1136,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, > (plane_state->view.color_plane[0].y + > (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { > plane_state->no_fbc_reason = "plane end Y offset misaligned"; > - return false; > + return 0; > } > > /* WaFbcExceedCdClockThreshold:hsw,bdw */ > -- > 2.35.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ff303c7d3a57..966970d1cf0a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1086,7 +1086,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, */ if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) { plane_state->no_fbc_reason = "PSR2 enabled"; - return false; + return 0; } if (!pixel_format_is_valid(plane_state)) { @@ -1112,7 +1112,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && fb->format->has_alpha) { plane_state->no_fbc_reason = "per-pixel alpha not supported"; - return false; + return 0; } if (!intel_fbc_hw_tracking_covers_screen(plane_state)) { @@ -1128,7 +1128,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, if (DISPLAY_VER(i915) >= 9 && plane_state->view.color_plane[0].y & 3) { plane_state->no_fbc_reason = "plane start Y offset misaligned"; - return false; + return 0; } /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ @@ -1136,7 +1136,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, (plane_state->view.color_plane[0].y + (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { plane_state->no_fbc_reason = "plane end Y offset misaligned"; - return false; + return 0; } /* WaFbcExceedCdClockThreshold:hsw,bdw */