| Message ID | 20220413192730.3608660-7-umesh.nerlige.ramappa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable compute and related WAs for DG2 | expand |
On 4/13/2022 12:27, Umesh Nerlige Ramappa wrote: > From: Tilak Tangudu <tilak.tangudu@intel.com> > > Prior to doing a reset, SW must ensure command streamer is stopped, > as a workaround, to eliminate a race condition in GPM flow. > Setting both the ring stop and prefetch disable bits, will cause the > command streamer to halt. > > v2: 1. Removed duplicate code and added only prefetch disable -Chris Wilson > > v3: 1. Applied wa for all gen12+ -Lahtinen Joonas/Vivi Rodrigo > > v4: 1. Added description in comment > 2. Added WA prior to read barrier-Chris Wilson > > v5: 1. Modified to disable prefetch and wait for idle ack -Chris Wilson Is this comment accurate? I'm not seeing a 'wait for idle ack' in the deltas. There is a wait for idle function but it is already present and not part of this patch change. > > Signed-off-by: Tilak Tangudu <tilak.tangudu@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 +++++++++ > drivers/gpu/drm/i915/gt/intel_engine_regs.h | 1 + > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 98b61ff13c95..14c6ddbbfde8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1280,6 +1280,15 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, > int err; > > intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); > + > + /* > + * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is > + * stopped, set ring stop bit and prefetch disable bit to halt CS > + */ > + if (GRAPHICS_VER(engine->i915) == 12) > + intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), > + _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); > + > err = __intel_wait_for_register_fw(engine->uncore, mode, > MODE_IDLE, MODE_IDLE, > fast_timeout_us, > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h > index 0bf8b45c9319..594a629cb28f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h > @@ -181,6 +181,7 @@ > #define GFX_SURFACE_FAULT_ENABLE (1 << 12) > #define GFX_REPLAY_MODE (1 << 11) > #define GFX_PSMI_GRANULARITY (1 << 10) > +#define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10) So the PSMI_GRANULARITY bit is not valid for Gen12 onwards? I'm not actually seeing it being used anywhere. So I guess it doesn't matte anyway! Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > #define GFX_PPGTT_ENABLE (1 << 9) > #define GEN8_GFX_PPGTT_48B (1 << 7) > #define GFX_FORWARD_VBLANK_MASK (3 << 5)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 98b61ff13c95..14c6ddbbfde8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1280,6 +1280,15 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine, int err; intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + + /* + * Wa_22011802037 : gen12, Prior to doing a reset, ensure CS is + * stopped, set ring stop bit and prefetch disable bit to halt CS + */ + if (GRAPHICS_VER(engine->i915) == 12) + intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base), + _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE)); + err = __intel_wait_for_register_fw(engine->uncore, mode, MODE_IDLE, MODE_IDLE, fast_timeout_us, diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index 0bf8b45c9319..594a629cb28f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -181,6 +181,7 @@ #define GFX_SURFACE_FAULT_ENABLE (1 << 12) #define GFX_REPLAY_MODE (1 << 11) #define GFX_PSMI_GRANULARITY (1 << 10) +#define GEN12_GFX_PREFETCH_DISABLE REG_BIT(10) #define GFX_PPGTT_ENABLE (1 << 9) #define GEN8_GFX_PPGTT_48B (1 << 7) #define GFX_FORWARD_VBLANK_MASK (3 << 5)