| Message ID | 20220504190756.466270-10-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/12] drm/i915: Drop IPC from display 13 and newer | expand |
On Wed, May 04, 2022 at 12:07:54PM -0700, José Roberto de Souza wrote: > No need to have this parameter in intel_device_info struct > as all platforms with display version 9 or newer has this feature. > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_pci.c | 3 --- > drivers/gpu/drm/i915/intel_device_info.h | 1 - > 3 files changed, 1 insertion(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 6b8a4e6649d9b..d8fa1d09cc828 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1303,7 +1303,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > IS_BROADWELL(dev_priv)) > #define HAS_DP_MST(dev_priv) (HAS_DDI(dev_priv)) > #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) > -#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > +#define HAS_PSR(dev_priv) (DISPLAY_VER(dev_priv) >= 9) > #define HAS_PSR_HW_TRACKING(dev_priv) \ > (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) > #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index d8b5e972109f9..098d47cc47b44 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -631,7 +631,6 @@ static const struct intel_device_info chv_info = { > GEN9_DEFAULT_PAGE_SIZES, \ > .display.has_dmc = 1, \ > .display.has_hdcp = 1, \ > - .display.has_psr = 1, \ > .display.has_psr_hw_tracking = 1, \ > .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ > .dbuf.slice_mask = BIT(DBUF_S1) > @@ -680,7 +679,6 @@ static const struct intel_device_info skl_gt4_info = { > .display.has_fpga_dbg = 1, \ > .display.fbc_mask = BIT(INTEL_FBC_A), \ > .display.has_hdcp = 1, \ > - .display.has_psr = 1, \ > .display.has_psr_hw_tracking = 1, \ > .has_runtime_pm = 1, \ > .display.has_dmc = 1, \ > @@ -928,7 +926,6 @@ static const struct intel_device_info adl_s_info = { > .display.has_fpga_dbg = 1, \ > .display.has_hdcp = 1, \ > .display.has_hotplug = 1, \ > - .display.has_psr = 1, \ > .display.ver = 13, \ > .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ > .pipe_offsets = { \ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index c4e85976d8948..5c17257f3f44b 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -174,7 +174,6 @@ enum intel_ppgtt_type { > func(has_hti); \ > func(has_modular_fia); \ > func(has_overlay); \ > - func(has_psr); \ > func(has_psr_hw_tracking); \ > func(overlay_needs_physical); \ > func(supports_tv); > -- > 2.36.0 >
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6b8a4e6649d9b..d8fa1d09cc828 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1303,7 +1303,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_BROADWELL(dev_priv)) #define HAS_DP_MST(dev_priv) (HAS_DDI(dev_priv)) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) -#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) +#define HAS_PSR(dev_priv) (DISPLAY_VER(dev_priv) >= 9) #define HAS_PSR_HW_TRACKING(dev_priv) \ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index d8b5e972109f9..098d47cc47b44 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -631,7 +631,6 @@ static const struct intel_device_info chv_info = { GEN9_DEFAULT_PAGE_SIZES, \ .display.has_dmc = 1, \ .display.has_hdcp = 1, \ - .display.has_psr = 1, \ .display.has_psr_hw_tracking = 1, \ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ .dbuf.slice_mask = BIT(DBUF_S1) @@ -680,7 +679,6 @@ static const struct intel_device_info skl_gt4_info = { .display.has_fpga_dbg = 1, \ .display.fbc_mask = BIT(INTEL_FBC_A), \ .display.has_hdcp = 1, \ - .display.has_psr = 1, \ .display.has_psr_hw_tracking = 1, \ .has_runtime_pm = 1, \ .display.has_dmc = 1, \ @@ -928,7 +926,6 @@ static const struct intel_device_info adl_s_info = { .display.has_fpga_dbg = 1, \ .display.has_hdcp = 1, \ .display.has_hotplug = 1, \ - .display.has_psr = 1, \ .display.ver = 13, \ .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .pipe_offsets = { \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index c4e85976d8948..5c17257f3f44b 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -174,7 +174,6 @@ enum intel_ppgtt_type { func(has_hti); \ func(has_modular_fia); \ func(has_overlay); \ - func(has_psr); \ func(has_psr_hw_tracking); \ func(overlay_needs_physical); \ func(supports_tv);
No need to have this parameter in intel_device_info struct as all platforms with display version 9 or newer has this feature. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 1 - 3 files changed, 1 insertion(+), 5 deletions(-)