| Message ID | 20220606060324.1618-1-anshuman.gupta@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dg2: Add Wa_14015795083 | expand |
On Mon, 06 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote: > i915 must disable Render DOP clock gating globally. > > B.Spec: 52621 Please use Bspec: BR, Jani. > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Badal Nilawar <badal.nilawar@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 58e9b464d564..55a291ab5536 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -630,6 +630,7 @@ > > #define GEN7_MISCCPCTL _MMIO(0x9424) > #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) > +#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE (1 << 1) > #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) > #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) > #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index a604bc7c0701..b957dec64eee 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1489,6 +1489,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > * performance guide section. > */ > wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); > + > + /* > + * Wa_14015795083 > + */ > + wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > } > > static void
> -----Original Message----- > From: Jani Nikula <jani.nikula@linux.intel.com> > Sent: Monday, June 6, 2022 1:53 PM > To: Gupta, Anshuman <anshuman.gupta@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_14015795083 > > On Mon, 06 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote: > > i915 must disable Render DOP clock gating globally. > > > > B.Spec: 52621 > > Please use > > Bspec: Thanks for pointing out, will fix this. Regards, Anshuman Gupta. > > BR, > Jani. > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Badal Nilawar <badal.nilawar@intel.com> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 58e9b464d564..55a291ab5536 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -630,6 +630,7 @@ > > > > #define GEN7_MISCCPCTL _MMIO(0x9424) > > #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) > > +#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE (1 << 1) > > #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) > > #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) > > #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index a604bc7c0701..b957dec64eee 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -1489,6 +1489,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, > struct i915_wa_list *wal) > > * performance guide section. > > */ > > wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); > > + > > + /* > > + * Wa_14015795083 > > + */ > > + wa_write_clr(wal, GEN7_MISCCPCTL, > GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > > } > > > > static void > > -- > Jani Nikula, Intel Open Source Graphics Center
On Mon, Jun 06, 2022 at 11:33:24AM +0530, Anshuman Gupta wrote: > i915 must disable Render DOP clock gating globally. > > B.Spec: 52621 > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Badal Nilawar <badal.nilawar@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 58e9b464d564..55a291ab5536 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -630,6 +630,7 @@ > > #define GEN7_MISCCPCTL _MMIO(0x9424) > #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) > +#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE (1 << 1) We should use a tab (instead of spaces) between the register name and the bit definition. We should probably switch to 'REG_BIT' notation for new bits being added too. > #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) > #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) > #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index a604bc7c0701..b957dec64eee 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1489,6 +1489,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > * performance guide section. > */ > wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); > + > + /* > + * Wa_14015795083 > + */ We can just use a single-line comment here. Aside from these cosmetic issues (and the formatting of 'Bspec' that Jani noted), Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > + wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > } > > static void > -- > 2.26.2 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 58e9b464d564..55a291ab5536 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -630,6 +630,7 @@ #define GEN7_MISCCPCTL _MMIO(0x9424) #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) +#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE (1 << 1) #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index a604bc7c0701..b957dec64eee 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1489,6 +1489,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) * performance guide section. */ wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); + + /* + * Wa_14015795083 + */ + wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); } static void
i915 must disable Render DOP clock gating globally. B.Spec: 52621 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ 2 files changed, 6 insertions(+)