From patchwork Thu Jun 16 12:05:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Dandamudi, Priyanka" X-Patchwork-Id: 12883796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5F4BC43334 for ; Thu, 16 Jun 2022 12:15:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B2B911A0A5; Thu, 16 Jun 2022 12:15:30 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 20BA111A0A5 for ; Thu, 16 Jun 2022 12:15:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655381728; x=1686917728; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=r7E0BLqPX6cDTmSrxZWfl0lOdn+ndFlUrOLeN9mhO5Y=; b=X5MY+xxZyy/s4ZsEjiMpdI1P5pWVXk20iWk5gShZdS9VS/HfJBJYoz9X zzFEa5g2NSOlJsH02IUmF9+Go0H7S9Yi922i6CaBsijdN3WLKjwCFVQA7 wLkJa6jLcWAmmiMBRJT+KDvucJcUga7n9T/EUccBXKd/c/L6z2CkdtQPm XxlS/c9LAHRex552hdhf8fTa9vOFT786sAOw1v9mTjf/bQjx1EWZtusKz YSQLex5iygaFSHpOLe57vrMNsV+EvDZpZmv2oZ5U6MJEttKTys6us2l7V RQUtxaheFpDi4xqWGWH1D8mUTuHqjKNN9OTZadwIr01lLLV1tajMUbHR0 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="278030920" X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="278030920" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 05:15:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,305,1647327600"; d="scan'208";a="831535787" Received: from priyanka-nuc7i7bnh.iind.intel.com ([10.145.162.209]) by fmsmga006.fm.intel.com with ESMTP; 16 Jun 2022 05:15:26 -0700 From: priyanka.dandamudi@intel.com To: priyanka.dandamudi@intel.com, matthew.auld@intel.com, intel-gfx@lists.freedesktop.org Date: Thu, 16 Jun 2022 17:35:08 +0530 Message-Id: <20220616120509.1190329-2-priyanka.dandamudi@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220616120509.1190329-1-priyanka.dandamudi@intel.com> References: <20220616120509.1190329-1-priyanka.dandamudi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 1/2] drm/i915: Add support for LMEM PCIe resizable bar X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Akeem G Abodunrin This patch adds support for the local memory PICe resizable bar, so that local memory can be resized to the maximum size supported by the device, and mapped correctly to the PCIe memory bar. It is usual that GPU devices expose only 256MB BARs primarily to be compatible with 32-bit systems. So, those devices cannot claim larger memory BAR windows size due to the system BIOS limitation. With this change, it would be possible to reprogram the windows of the bridge directly above the requesting device on the same BAR type. Signed-off-by: Akeem G Abodunrin Signed-off-by: Michał Winiarski Cc: Stuart Summers Cc: Michael J Ruhl Cc: Prathap Kumar Valsan Signed-off-by: Priyanka Dandamudi Reviewed-by: Matthew Auld Reported-by: kernel test robot --- drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index d26dcca7e654..4bdb471cb2e2 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915) __intel_gt_reset(to_gt(i915), ALL_ENGINES); } +static void __release_bars(struct pci_dev *pdev) +{ + int resno; + + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) { + if (pci_resource_len(pdev, resno)) + pci_release_resource(pdev, resno); + } +} + +static void +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size) +{ + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + int bar_size = pci_rebar_bytes_to_size(size); + int ret; + + __release_bars(pdev); + + ret = pci_resize_resource(pdev, resno, bar_size); + if (ret) { + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n", + resno, 1 << bar_size, ERR_PTR(ret)); + return; + } + + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); +} + +/* BAR size starts from 1MB - 2^20 */ +#define BAR_SIZE_SHIFT 20 +static resource_size_t +__lmem_rebar_size(struct drm_i915_private *i915, int resno) +{ + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno); + resource_size_t size; + + if (!rebar) + return 0; + + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT); + + if (size <= pci_resource_len(pdev, resno)) + return 0; + + return size; +} + +#define LMEM_BAR_NUM 2 +static void i915_resize_lmem_bar(struct drm_i915_private *i915) +{ + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + struct pci_bus *root = pdev->bus; + struct resource *root_res; + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM); + u32 pci_cmd; + int i; + + if (!rebar_size) + return; + + /* Find out if root bus contains 64bit memory addressing */ + while (root->parent) + root = root->parent; + + pci_bus_for_each_resource(root, root_res, i) { + if (root_res && root_res->flags & (IORESOURCE_MEM | + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull) + break; + } + + /* pci_resize_resource will fail anyways */ + if (!root_res) { + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n"); + return; + } + + /* First disable PCI memory decoding references */ + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd); + pci_write_config_dword(pdev, PCI_COMMAND, + pci_cmd & ~PCI_COMMAND_MEMORY); + + __resize_bar(i915, LMEM_BAR_NUM, rebar_size); + + pci_assign_unassigned_bus_resources(pdev->bus); + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); +} + /** * i915_driver_early_probe - setup state not requiring device access * @dev_priv: device private @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) disable_rpm_wakeref_asserts(&i915->runtime_pm); + if (HAS_LMEM(i915)) + i915_resize_lmem_bar(i915); + intel_vgpu_detect(i915); ret = intel_gt_probe_all(i915);