| Message ID | 20220623144955.2486736-1-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/fourcc: Document the Intel CCS modifiers' CC plane expected pitch | expand |
+Jordan (FYI) I think the commit message has an extra "color" next to "CC". With or without that dropped, Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Thanks for the fix. > -----Original Message----- > From: Deak, Imre <imre.deak@intel.com> > Sent: Thursday, June 23, 2022 10:50 AM > To: dri-devel@lists.freedesktop.org > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G <nanley.g.chery@intel.com> > Subject: [PATCH] drm/fourcc: Document the Intel CCS modifiers' CC plane expected pitch > > The driver expects the pitch of the Intel CCS CC color planes to be > 64 bytes aligned, adjust the modifier descriptions accordingly. > > Cc: Nanley Chery <nanley.g.chery@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > include/uapi/drm/drm_fourcc.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index f1972154a5940..c1b4cfda75075 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -559,7 +559,7 @@ extern "C" { > * > * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear > * and at index 1. The clear color is stored at index 2, and the pitch should > - * be ignored. The clear color structure is 256 bits. The first 128 bits > + * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits > * represents Raw Clear Color Red, Green, Blue and Alpha color each represented > * by 32 bits. The raw clear color is consumed by the 3d engine and generates > * the converted clear color of size 64 bits. The first 32 bits store the Lower > @@ -612,9 +612,9 @@ extern "C" { > * outside of the GEM object in a reserved memory area dedicated for the > * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The > * main surface pitch is required to be a multiple of four Tile 4 widths. The > - * clear color is stored at plane index 1 and the pitch should be ignored. The > - * format of the 256 bits of clear color data matches the one used for the > - * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description > + * clear color is stored at plane index 1 and the pitch should be 64 bytes > + * aligned. The format of the 256 bits of clear color data matches the one used > + * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description > * for details. > */ > #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) > -- > 2.30.2
Actually add Jordan this time :) > -----Original Message----- > From: Chery, Nanley G > Sent: Friday, June 24, 2022 5:39 PM > To: Deak, Imre <imre.deak@intel.com>; dri-devel@lists.freedesktop.org > Cc: intel-gfx@lists.freedesktop.org > Subject: RE: [PATCH] drm/fourcc: Document the Intel CCS modifiers' CC plane expected pitch > > +Jordan (FYI) > > I think the commit message has an extra "color" next to "CC". > With or without that dropped, > > Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> > > Thanks for the fix. > > > -----Original Message----- > > From: Deak, Imre <imre.deak@intel.com> > > Sent: Thursday, June 23, 2022 10:50 AM > > To: dri-devel@lists.freedesktop.org > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G <nanley.g.chery@intel.com> > > Subject: [PATCH] drm/fourcc: Document the Intel CCS modifiers' CC plane expected pitch > > > > The driver expects the pitch of the Intel CCS CC color planes to be > > 64 bytes aligned, adjust the modifier descriptions accordingly. > > > > Cc: Nanley Chery <nanley.g.chery@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > include/uapi/drm/drm_fourcc.h | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > > index f1972154a5940..c1b4cfda75075 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -559,7 +559,7 @@ extern "C" { > > * > > * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear > > * and at index 1. The clear color is stored at index 2, and the pitch should > > - * be ignored. The clear color structure is 256 bits. The first 128 bits > > + * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits > > * represents Raw Clear Color Red, Green, Blue and Alpha color each represented > > * by 32 bits. The raw clear color is consumed by the 3d engine and generates > > * the converted clear color of size 64 bits. The first 32 bits store the Lower > > @@ -612,9 +612,9 @@ extern "C" { > > * outside of the GEM object in a reserved memory area dedicated for the > > * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The > > * main surface pitch is required to be a multiple of four Tile 4 widths. The > > - * clear color is stored at plane index 1 and the pitch should be ignored. The > > - * format of the 256 bits of clear color data matches the one used for the > > - * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description > > + * clear color is stored at plane index 1 and the pitch should be 64 bytes > > + * aligned. The format of the 256 bits of clear color data matches the one used > > + * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description > > * for details. > > */ > > #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) > > -- > > 2.30.2
On 2022-06-24 14:38:50, Chery, Nanley G wrote: > +Jordan (FYI) > > I think the commit message has an extra "color" next to "CC". > With or without that dropped, > > Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
On Sat, Jun 25, 2022 at 12:38:50AM +0300, Chery, Nanley G wrote: > +Jordan (FYI) > > I think the commit message has an extra "color" next to "CC". IIUC, i915 calls all the planes contained in a framebuffer "color planes" for consistency (so main-, aux-, CC color planes). > With or without that dropped, > > Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> The patch is pushed to drm-misc-next, thanks for the reviews. --Imre > Thanks for the fix. > > > -----Original Message----- > > From: Deak, Imre <imre.deak@intel.com> > > Sent: Thursday, June 23, 2022 10:50 AM > > To: dri-devel@lists.freedesktop.org > > Cc: intel-gfx@lists.freedesktop.org; Chery, Nanley G <nanley.g.chery@intel.com> > > Subject: [PATCH] drm/fourcc: Document the Intel CCS modifiers' CC plane expected pitch > > > > The driver expects the pitch of the Intel CCS CC color planes to be > > 64 bytes aligned, adjust the modifier descriptions accordingly. > > > > Cc: Nanley Chery <nanley.g.chery@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > include/uapi/drm/drm_fourcc.h | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > > index f1972154a5940..c1b4cfda75075 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -559,7 +559,7 @@ extern "C" { > > * > > * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear > > * and at index 1. The clear color is stored at index 2, and the pitch should > > - * be ignored. The clear color structure is 256 bits. The first 128 bits > > + * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits > > * represents Raw Clear Color Red, Green, Blue and Alpha color each represented > > * by 32 bits. The raw clear color is consumed by the 3d engine and generates > > * the converted clear color of size 64 bits. The first 32 bits store the Lower > > @@ -612,9 +612,9 @@ extern "C" { > > * outside of the GEM object in a reserved memory area dedicated for the > > * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The > > * main surface pitch is required to be a multiple of four Tile 4 widths. The > > - * clear color is stored at plane index 1 and the pitch should be ignored. The > > - * format of the 256 bits of clear color data matches the one used for the > > - * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description > > + * clear color is stored at plane index 1 and the pitch should be 64 bytes > > + * aligned. The format of the 256 bits of clear color data matches the one used > > + * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description > > * for details. > > */ > > #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) > > -- > > 2.30.2 >
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index f1972154a5940..c1b4cfda75075 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -559,7 +559,7 @@ extern "C" { * * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear * and at index 1. The clear color is stored at index 2, and the pitch should - * be ignored. The clear color structure is 256 bits. The first 128 bits + * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits * represents Raw Clear Color Red, Green, Blue and Alpha color each represented * by 32 bits. The raw clear color is consumed by the 3d engine and generates * the converted clear color of size 64 bits. The first 32 bits store the Lower @@ -612,9 +612,9 @@ extern "C" { * outside of the GEM object in a reserved memory area dedicated for the * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The * main surface pitch is required to be a multiple of four Tile 4 widths. The - * clear color is stored at plane index 1 and the pitch should be ignored. The - * format of the 256 bits of clear color data matches the one used for the - * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description + * clear color is stored at plane index 1 and the pitch should be 64 bytes + * aligned. The format of the 256 bits of clear color data matches the one used + * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description * for details. */ #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
The driver expects the pitch of the Intel CCS CC color planes to be 64 bytes aligned, adjust the modifier descriptions accordingly. Cc: Nanley Chery <nanley.g.chery@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- include/uapi/drm/drm_fourcc.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)