From patchwork Wed Jun 29 11:29:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Usyskin, Alexander" X-Patchwork-Id: 12899826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ABCE5C43334 for ; Wed, 29 Jun 2022 11:29:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E79DD112FC4; Wed, 29 Jun 2022 11:29:44 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 60AB2112FC4 for ; Wed, 29 Jun 2022 11:29:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656502184; x=1688038184; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Y9U1WhJAWoCyuEBJ9cdgbIqAVPEHAMhulLIhS8kamw=; b=c2LUfG7Iw9E/QY1fA0U3b6UXvww7cbAlR/ipacZFNpHbpg8fqH4htfVl hGMixuXEsPYBjBk6wXqiMnVIZK0mIIzGaRYSKY00+YrG7NzL2dvIUydVi gAxH/1FM/9HugyBTznOnvtfi3MZ0DhfpgsXuYtRh7l6Z/fvPuZvWOVF81 RZkuOB/8nWTxdDo8/2Zb5JqBBn7YGYfkAbcbb041PteVWVyq2amD30FAb K0QVCZKM9DjurMglPW7/Jo4Q91TKZzjdW7ecF7+h/CgtSQzFuf83SVikH SU4596D8TZ3QG7C0BpYSnJXEfH+prJtZynQi3dWFijgtCLuVG3G0mFPn/ A==; X-IronPort-AV: E=McAfee;i="6400,9594,10392"; a="368319257" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="368319257" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 04:29:43 -0700 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="647353096" Received: from sannilnx.jer.intel.com ([10.12.26.157]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 04:29:41 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , David Airlie , Daniel Vetter , Tvrtko Ursulin Date: Wed, 29 Jun 2022 14:29:04 +0300 Message-Id: <20220629112913.1210933-6-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629112913.1210933-1-alexander.usyskin@intel.com> References: <20220629112913.1210933-1-alexander.usyskin@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 05/14] drm/i915/gsc: add GSC XeHP SDV platform definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Define GSC on XeHP SDV (Intel(R) dGPU without display) XeHP SDV uses the same hardware settings as DG1, but uses polling instead of interrupts and runs the firmware in slow pace due to hardware limitations. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c index f963c220bbff..bfc307e49bf9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = { } }; +static const struct gsc_def gsc_def_xehpsdv[] = { + { + /* HECI1 not enabled on the device. */ + }, + { + .name = "mei-gscfi", + .bar = DG1_GSC_HECI2_BASE, + .bar_size = GSC_BAR_LENGTH, + .use_polling = true, + .slow_fw = true, + } +}; + static const struct gsc_def gsc_def_dg2[] = { { .name = "mei-gsc", @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915, if (IS_DG1(i915)) { def = &gsc_def_dg1[intf_id]; + } else if (IS_XEHPSDV(i915)) { + def = &gsc_def_xehpsdv[intf_id]; } else if (IS_DG2(i915)) { def = &gsc_def_dg2[intf_id]; } else {