diff mbox series

drm/i915/tc: Fix PHY ownership programming in HDMI legacy mode

Message ID 20220726134313.1484763-1-imre.deak@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/tc: Fix PHY ownership programming in HDMI legacy mode | expand

Commit Message

Imre Deak July 26, 2022, 1:43 p.m. UTC
Make sure the TypeC PHY ownership flag is not getting reset during
an HDMI modeset on the given port. Besides the WARN this triggered, it
didn't cause other issues, since for TypeC legacy mode setting the
PHY ownership flag is optional (there is no other user of the PHY
besides display).

Reported-and-tested-by: Shawn C Lee <shawn.c.lee@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Kahola, Mika Aug. 12, 2022, 7:27 a.m. UTC | #1
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre
> Deak
> Sent: Tuesday, July 26, 2022 4:43 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH] drm/i915/tc: Fix PHY ownership programming in
> HDMI legacy mode
> 
> Make sure the TypeC PHY ownership flag is not getting reset during an HDMI
> modeset on the given port. Besides the WARN this triggered, it didn't cause
> other issues, since for TypeC legacy mode setting the PHY ownership flag is
> optional (there is no other user of the PHY besides display).
> 
> Reported-and-tested-by: Shawn C Lee <shawn.c.lee@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a4c8493f3ce77..6c43a5124cb8e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2866,6 +2866,8 @@ static void intel_enable_ddi_hdmi(struct
> intel_atomic_state *state,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_connector *connector = conn_state->connector;
>  	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
> +	u32 buf_ctl;
> 
>  	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
>  					       crtc_state-
> >hdmi_high_tmds_clock_ratio,
> @@ -2923,8 +2925,12 @@ static void intel_enable_ddi_hdmi(struct
> intel_atomic_state *state,
>  	 * On ADL_P the PHY link rate and lane count must be programmed but
>  	 * these are both 0 for HDMI.
>  	 */
> -	intel_de_write(dev_priv, DDI_BUF_CTL(port),
> -		       dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
> +	buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> +	if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> +		drm_WARN_ON(&dev_priv->drm,
> !intel_tc_port_in_legacy_mode(dig_port));
> +		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +	}
> +	intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> 
>  	intel_audio_codec_enable(encoder, crtc_state, conn_state);  }
> --
> 2.34.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4c8493f3ce77..6c43a5124cb8e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2866,6 +2866,8 @@  static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_connector *connector = conn_state->connector;
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+	u32 buf_ctl;
 
 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
 					       crtc_state->hdmi_high_tmds_clock_ratio,
@@ -2923,8 +2925,12 @@  static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 	 * On ADL_P the PHY link rate and lane count must be programmed but
 	 * these are both 0 for HDMI.
 	 */
-	intel_de_write(dev_priv, DDI_BUF_CTL(port),
-		       dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
+	buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
+	if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
+		drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
+		buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+	}
+	intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
 
 	intel_audio_codec_enable(encoder, crtc_state, conn_state);
 }