| Message ID | 20220728183641.55692-1-anusha.srivatsa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [CI] drm/i915/dg2: Add support for DC5 state | expand |
On Thu, Jul 28, 2022 at 11:36:41AM -0700, Anusha Srivatsa wrote: > With the latest DMC in place, enabling DC5 on DG2. > > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Thanks for the patch, pushed to drm-intel-next. The failures in the IGT CI result are unrelated, since there are no shard-DG2 machines. > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 13aaa3247a5a..3f84af6beff3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -908,7 +908,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, > return 0; > > if (IS_DG2(dev_priv)) > - max_dc = 0; > + max_dc = 1; > else if (IS_DG1(dev_priv)) > max_dc = 3; > else if (DISPLAY_VER(dev_priv) >= 12) > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 13aaa3247a5a..3f84af6beff3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -908,7 +908,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, return 0; if (IS_DG2(dev_priv)) - max_dc = 0; + max_dc = 1; else if (IS_DG1(dev_priv)) max_dc = 3; else if (DISPLAY_VER(dev_priv) >= 12)
With the latest DMC in place, enabling DC5 on DG2. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)