| Message ID | 20220818234202.451742-15-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Initial Meteorlake Support | expand |
On Thu, Aug 18, 2022 at 04:41:55PM -0700, Radhakrishna Sripada wrote: > Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers > instead of GT driver mailbox. > > v2: Use the extracted wm latency adjustment function(Matt) > > Bspec: 64608 > > Cc: Matt Roper <matthew.d.roper@intel.com> > Original Author: Caz Yokoyama > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > drivers/gpu/drm/i915/intel_pm.c | 21 ++++++++++++++++++--- > 2 files changed, 25 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 04a269fa8717..b2d5e1230c25 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8390,4 +8390,11 @@ enum skl_power_gate { > #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) > > #define MTL_MEDIA_GSI_BASE 0x380000 > + > +#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) > +#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) > +#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) > +#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0) > +#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16) You might consider "_{EVEN,ODD}_LEVEL_MASK" naming here, just in case future IP versions add additional levels beyond LP5. Otherwise, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > + > #endif /* _I915_REG_H_ */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 898e56d2eaf7..fac565d23d57 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2908,13 +2908,28 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, > u16 wm[]) > { > struct intel_uncore *uncore = &dev_priv->uncore; > + int max_level = ilk_wm_max_level(dev_priv); > > - if (DISPLAY_VER(dev_priv) >= 9) { > + if (DISPLAY_VER(dev_priv) >= 14) { > + u32 val; > + > + val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1); > + wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); > + wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); > + val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3); > + wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); > + wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); > + val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5); > + wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); > + wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); > + > + adjust_wm_latency(wm, max_level, 6, > + dev_priv->dram_info.wm_lv_0_adjust_needed); > + } else if (DISPLAY_VER(dev_priv) >= 9) { > int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2; > + int mult = IS_DG2(dev_priv) ? 2 : 1; > u32 val; > int ret; > - int max_level = ilk_wm_max_level(dev_priv); > - int mult = IS_DG2(dev_priv) ? 2 : 1; > > /* read the first set of memory latencies[0:3] */ > val = 0; /* data0 to be programmed to 0 for first set */ > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04a269fa8717..b2d5e1230c25 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8390,4 +8390,11 @@ enum skl_power_gate { #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) #define MTL_MEDIA_GSI_BASE 0x380000 + +#define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) +#define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) +#define MTL_LATENCY_LP4_LP5 _MMIO(0x45788) +#define MTL_LATENCY_LEVEL0_2_4_MASK REG_GENMASK(12, 0) +#define MTL_LATENCY_LEVEL1_3_5_MASK REG_GENMASK(28, 16) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 898e56d2eaf7..fac565d23d57 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2908,13 +2908,28 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, u16 wm[]) { struct intel_uncore *uncore = &dev_priv->uncore; + int max_level = ilk_wm_max_level(dev_priv); - if (DISPLAY_VER(dev_priv) >= 9) { + if (DISPLAY_VER(dev_priv) >= 14) { + u32 val; + + val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1); + wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3); + wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5); + wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL0_2_4_MASK, val); + wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL1_3_5_MASK, val); + + adjust_wm_latency(wm, max_level, 6, + dev_priv->dram_info.wm_lv_0_adjust_needed); + } else if (DISPLAY_VER(dev_priv) >= 9) { int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2; + int mult = IS_DG2(dev_priv) ? 2 : 1; u32 val; int ret; - int max_level = ilk_wm_max_level(dev_priv); - int mult = IS_DG2(dev_priv) ? 2 : 1; /* read the first set of memory latencies[0:3] */ val = 0; /* data0 to be programmed to 0 for first set */
Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers instead of GT driver mailbox. v2: Use the extracted wm latency adjustment function(Matt) Bspec: 64608 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ drivers/gpu/drm/i915/intel_pm.c | 21 ++++++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-)