diff mbox series

drm/i915/combo_phy: Set DCC_MODE to one time update mode

Message ID 20220822122513.3607326-1-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/combo_phy: Set DCC_MODE to one time update mode | expand

Commit Message

Nautiyal, Ankit K Aug. 22, 2022, 12:25 p.m. UTC 
As per Bspec:49291 update, the DCC Mode select is to be set to one time
update mode, instead of continuous DCC calibration mode for Display > 12
combo phy.

This change is required to avoid glitches that occur, during on the fly
updates to DCC code, with continuous mode, resulting in flickers seen with
eDP HBR3 panels.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_combo_phy_regs.h | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 64890f39c3cc..76e4e748823a 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -244,7 +244,7 @@  static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 
 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
 				     DCC_MODE_SELECT_MASK,
-				     DCC_MODE_SELECT_CONTINUOSLY);
+				     DCC_MODE_SELECT_ONCE);
 	}
 
 	ret &= icl_verify_procmon_ref_values(dev_priv, phy);
@@ -367,7 +367,7 @@  static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 
 			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
 			val &= ~DCC_MODE_SELECT_MASK;
-			val |= DCC_MODE_SELECT_CONTINUOSLY;
+			val |= DCC_MODE_SELECT_ONCE;
 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
 		}
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
index 2ed65193ca19..cf46f13401d1 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
@@ -92,6 +92,7 @@ 
 #define ICL_PORT_PCS_DW1_LN(ln, phy)		_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
 #define   DCC_MODE_SELECT_MASK			(0x3 << 20)
 #define   DCC_MODE_SELECT_CONTINUOSLY		(0x3 << 20)
+#define   DCC_MODE_SELECT_ONCE			(0x0 << 20)
 #define   COMMON_KEEPER_EN			(1 << 26)
 #define   LATENCY_OPTIM_MASK			(0x3 << 2)
 #define   LATENCY_OPTIM_VAL(x)			((x) << 2)