@@ -3923,6 +3923,14 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ /*
+ * No need to update mask value/restrict because
+ * "Pcode only wants to use GV bandwidth value, not the mask value."
+ * for DISPLAY_VER() >= 14.
+ */
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
@@ -3943,6 +3951,16 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
+ /*
+ * No need to update mask value/restrict because
+ * "Pcode only wants to use GV bandwidth value, not the mask value."
+ * for DISPLAY_VER() >= 14.
+ *
+ * GV bandwidth will be set by intel_pmdemand_post_plane_update()
+ */
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
Display 14 and future platforms do not directly communicate to Pcode via mailbox the SAGV bandwidth information. PM Demand registers are used to communicate display power requirements to the PUnit which would include GV point and mask value. Skip programming GV point and mask values through legacy pcode mailbox interface. Bspec: 64636 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)