| Message ID | 20220909025646.3397620-7-badal.nilawar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | i915: CAGF and RC6 changes for MTL | expand |
On Thu, 08 Sep 2022 19:56:46 -0700, Badal Nilawar wrote: > > For MTL SAMedia updated relevant functions and places in the code to get > Media C6 residency. > > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> > Cc: Chris Wilson <chris.p.wilson@intel.com> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10 ++++ > drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++- > drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- > drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++- > drivers/gpu/drm/i915/i915_pmu.c | 8 ++- > 6 files changed, 93 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > index 96c03a1258e1..6913c0a2ba33 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > @@ -269,6 +269,60 @@ static int ilk_drpc(struct seq_file *m) > return 0; > } > > +static int mtl_drpc(struct seq_file *m) > +{ > + struct intel_gt *gt = m->private; > + struct intel_uncore *uncore = gt->uncore; > + u32 gt_core_status, rcctl1; > + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0; > + i915_reg_t reg; > + Comparing with gen6_drpc do we need to add this here: mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); And show it later as in gen6_drpc? > + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); > + > + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); > + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); > + mtl_powergate_status = intel_uncore_read(uncore, > + GEN9_PWRGT_DOMAIN_STATUS); > + > + seq_printf(m, "RC6 Enabled: %s\n", > + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); > + if (gt->type == GT_MEDIA) { > + seq_printf(m, "Media Well Gating Enabled: %s\n", > + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE)); > + } else { > + seq_printf(m, "Render Well Gating Enabled: %s\n", > + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE)); > + } > + > + seq_puts(m, "Current RC state: "); > + > + switch ((gt_core_status & MTL_CC_MASK) >> MTL_CC_SHIFT) { > + case MTL_CC0: > + seq_puts(m, "on\n"); > + break; > + case MTL_CC6: > + seq_puts(m, "RC6\n"); > + break; > + default: > + seq_puts(m, "Unknown\n"); > + break; > + } > + > + if (gt->type == GT_MEDIA) > + seq_printf(m, "Media Power Well: %s\n", > + (mtl_powergate_status & > + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); > + else > + seq_printf(m, "Render Power Well: %s\n", > + (mtl_powergate_status & > + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); > + > + reg = (gt->type == GT_MEDIA) ? MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6; > + print_rc6_res(m, "RC6 residency since boot:", reg); > + > + return fw_domains_show(m, NULL); > +} > + > static int drpc_show(struct seq_file *m, void *unused) > { > struct intel_gt *gt = m->private; > @@ -279,6 +333,8 @@ static int drpc_show(struct seq_file *m, void *unused) > with_intel_runtime_pm(gt->uncore->rpm, wakeref) { > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > err = vlv_drpc(m); > + else if (MEDIA_VER(i915) >= 13) Why a MEDIA_VER check here? Should we use 'if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))' or 'IS_METEORLAKE'? > + err = mtl_drpc(m); > else if (GRAPHICS_VER(i915) >= 6) > err = gen6_drpc(m); > else > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index ab9a5e66ab34..2c6cf29888e0 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1522,6 +1522,16 @@ > */ > #define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60) > #define MTL_CAGF_MASK REG_GENMASK(8, 0) > +#define MTL_CC0 0x0 > +#define MTL_CC6 0x3 > +#define MTL_CC_SHIFT 9 > +#define MTL_CC_MASK (0xf << MTL_CC_SHIFT) Let's remove MTL_CC_SHIFT and do #define MTL_CC_MASK REG_GENMASK(12, 9) Above where we are using these just use REG_FIELD_GET(MTL_CC_MASK, gt_core_status). > + > +/* > + * MTL: This register contains the total MC6 residency time that SAMedia was > + * since boot > + */ > +#define MTL_MEDIA_MC6 _MMIO(0x138048) > > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) > #define GEN11_CSME (31) > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > index e066cc33d9f2..fb2cf8ee2eeb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c > @@ -138,7 +138,14 @@ static ssize_t rc6_residency_ms_show(struct device *dev, > > static u32 __rc6p_residency_ms_show(struct intel_gt *gt) > { > - return get_residency(gt, GEN6_GT_GFX_RC6p); > + i915_reg_t reg; > + > + if (gt->type == GT_MEDIA) > + reg = MTL_MEDIA_MC6; > + else > + reg = GEN6_GT_GFX_RC6; > + > + return get_residency(gt, reg); This is not right, did you mean to make this change to __rc6_residency_ms_show? > } > > static ssize_t rc6p_residency_ms_show(struct device *dev, > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index f8d0523f4c18..26f71f7f07c6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -745,6 +745,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) > unsigned long flags; > unsigned int i; > u32 mul, div; > + i915_reg_t base; > > if (!rc6->supported) > return 0; > @@ -756,8 +757,10 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) > * other so we can use the relative address, compared to the smallest > * one as the index into driver storage. > */ > + base = (rc6_to_gt(rc6)->type == GT_MEDIA) ? > + MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6_LOCKED; > i = (i915_mmio_reg_offset(reg) - > - i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); > + i915_mmio_reg_offset(base)) / sizeof(u32); > if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) > return 0; > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c > index 8c70b7e12074..28c6a4b6b8d1 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c > @@ -15,11 +15,18 @@ > > static u64 rc6_residency(struct intel_rc6 *rc6) > { > + struct intel_gt *gt = rc6_to_gt(rc6); > + i915_reg_t reg; > u64 result; > > /* XXX VLV_GT_MEDIA_RC6? */ > > - result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6); > + if (gt->type == GT_MEDIA) > + reg = MTL_MEDIA_MC6; > + else > + reg = GEN6_GT_GFX_RC6; > + > + result = intel_rc6_residency_ns(rc6, reg); > if (HAS_RC6p(rc6_to_i915(rc6))) > result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p); > if (HAS_RC6pp(rc6_to_i915(rc6))) > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index a24704ec2c18..3653e542cbf8 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -146,9 +146,15 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) > static u64 __get_rc6(struct intel_gt *gt) > { > struct drm_i915_private *i915 = gt->i915; > + i915_reg_t reg; > u64 val; > > - val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6); > + if (gt->type == GT_MEDIA) > + reg = MTL_MEDIA_MC6; > + else > + reg = GEN6_GT_GFX_RC6; > + > + val = intel_rc6_residency_ns(>->rc6, reg); > > if (HAS_RC6p(i915)) > val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p); > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 96c03a1258e1..6913c0a2ba33 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -269,6 +269,60 @@ static int ilk_drpc(struct seq_file *m) return 0; } +static int mtl_drpc(struct seq_file *m) +{ + struct intel_gt *gt = m->private; + struct intel_uncore *uncore = gt->uncore; + u32 gt_core_status, rcctl1; + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0; + i915_reg_t reg; + + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); + + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); + mtl_powergate_status = intel_uncore_read(uncore, + GEN9_PWRGT_DOMAIN_STATUS); + + seq_printf(m, "RC6 Enabled: %s\n", + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); + if (gt->type == GT_MEDIA) { + seq_printf(m, "Media Well Gating Enabled: %s\n", + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE)); + } else { + seq_printf(m, "Render Well Gating Enabled: %s\n", + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE)); + } + + seq_puts(m, "Current RC state: "); + + switch ((gt_core_status & MTL_CC_MASK) >> MTL_CC_SHIFT) { + case MTL_CC0: + seq_puts(m, "on\n"); + break; + case MTL_CC6: + seq_puts(m, "RC6\n"); + break; + default: + seq_puts(m, "Unknown\n"); + break; + } + + if (gt->type == GT_MEDIA) + seq_printf(m, "Media Power Well: %s\n", + (mtl_powergate_status & + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); + else + seq_printf(m, "Render Power Well: %s\n", + (mtl_powergate_status & + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); + + reg = (gt->type == GT_MEDIA) ? MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6; + print_rc6_res(m, "RC6 residency since boot:", reg); + + return fw_domains_show(m, NULL); +} + static int drpc_show(struct seq_file *m, void *unused) { struct intel_gt *gt = m->private; @@ -279,6 +333,8 @@ static int drpc_show(struct seq_file *m, void *unused) with_intel_runtime_pm(gt->uncore->rpm, wakeref) { if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) err = vlv_drpc(m); + else if (MEDIA_VER(i915) >= 13) + err = mtl_drpc(m); else if (GRAPHICS_VER(i915) >= 6) err = gen6_drpc(m); else diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index ab9a5e66ab34..2c6cf29888e0 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1522,6 +1522,16 @@ */ #define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60) #define MTL_CAGF_MASK REG_GENMASK(8, 0) +#define MTL_CC0 0x0 +#define MTL_CC6 0x3 +#define MTL_CC_SHIFT 9 +#define MTL_CC_MASK (0xf << MTL_CC_SHIFT) + +/* + * MTL: This register contains the total MC6 residency time that SAMedia was + * since boot + */ +#define MTL_MEDIA_MC6 _MMIO(0x138048) #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) #define GEN11_CSME (31) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index e066cc33d9f2..fb2cf8ee2eeb 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@ -138,7 +138,14 @@ static ssize_t rc6_residency_ms_show(struct device *dev, static u32 __rc6p_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, GEN6_GT_GFX_RC6p); + i915_reg_t reg; + + if (gt->type == GT_MEDIA) + reg = MTL_MEDIA_MC6; + else + reg = GEN6_GT_GFX_RC6; + + return get_residency(gt, reg); } static ssize_t rc6p_residency_ms_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index f8d0523f4c18..26f71f7f07c6 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -745,6 +745,7 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) unsigned long flags; unsigned int i; u32 mul, div; + i915_reg_t base; if (!rc6->supported) return 0; @@ -756,8 +757,10 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) * other so we can use the relative address, compared to the smallest * one as the index into driver storage. */ + base = (rc6_to_gt(rc6)->type == GT_MEDIA) ? + MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6_LOCKED; i = (i915_mmio_reg_offset(reg) - - i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); + i915_mmio_reg_offset(base)) / sizeof(u32); if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) return 0; diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 8c70b7e12074..28c6a4b6b8d1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -15,11 +15,18 @@ static u64 rc6_residency(struct intel_rc6 *rc6) { + struct intel_gt *gt = rc6_to_gt(rc6); + i915_reg_t reg; u64 result; /* XXX VLV_GT_MEDIA_RC6? */ - result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6); + if (gt->type == GT_MEDIA) + reg = MTL_MEDIA_MC6; + else + reg = GEN6_GT_GFX_RC6; + + result = intel_rc6_residency_ns(rc6, reg); if (HAS_RC6p(rc6_to_i915(rc6))) result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p); if (HAS_RC6pp(rc6_to_i915(rc6))) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index a24704ec2c18..3653e542cbf8 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -146,9 +146,15 @@ static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active) static u64 __get_rc6(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; + i915_reg_t reg; u64 val; - val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6); + if (gt->type == GT_MEDIA) + reg = MTL_MEDIA_MC6; + else + reg = GEN6_GT_GFX_RC6; + + val = intel_rc6_residency_ns(>->rc6, reg); if (HAS_RC6p(i915)) val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
For MTL SAMedia updated relevant functions and places in the code to get Media C6 residency. Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com> Cc: Chris Wilson <chris.p.wilson@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10 ++++ drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++- drivers/gpu/drm/i915/i915_pmu.c | 8 ++- 6 files changed, 93 insertions(+), 4 deletions(-)