From patchwork Wed Sep 21 07:09:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niranjana Vishwanathapura X-Patchwork-Id: 12983285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 405C1C32771 for ; Wed, 21 Sep 2022 07:11:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 538D010E86A; Wed, 21 Sep 2022 07:10:22 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 27C3410E85C; Wed, 21 Sep 2022 07:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663744212; x=1695280212; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HfSM5dHkfqRV7ird2JhTynUHOeKJUWeYULIA6WSxruc=; b=KlQ2/j63lCuLpm6aNUCMI1oaSjDIRm9CJptm+Aw4fC1bNzDysnI6+5vy /lqmb1ugFyqxcAw6vgXC/ImhdS3mBhdB97ZsqzPEzaOGFhM9+svPpq1Ly mE07k3WXUew6GqmdtjolKek1gTmw+sf89fKTVyVd7cLGL8GUcwu1Z9qO0 GeeCub8SZEalLKSUpPHQaSjkOQNPPR6Lb/jBFNKpzqbDtZToLX9yUibER 1jw0js56XqcSssuAMI4Yt6GWizIgmbYeH6Uu9+yKDmvNZI8DrbwJYoBuo XgvWw/JNQQktG6ZsvqtmdilB+620H1TZJjwC2DomANGUCeedu4w75RstG g==; X-IronPort-AV: E=McAfee;i="6500,9779,10476"; a="386208166" X-IronPort-AV: E=Sophos;i="5.93,332,1654585200"; d="scan'208";a="386208166" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 00:10:11 -0700 X-IronPort-AV: E=Sophos;i="5.93,332,1654585200"; d="scan'208";a="948022807" Received: from nvishwa1-desk.sc.intel.com ([172.25.29.76]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-SHA; 21 Sep 2022 00:10:11 -0700 From: Niranjana Vishwanathapura To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Wed, 21 Sep 2022 00:09:33 -0700 Message-Id: <20220921070945.27764-3-niranjana.vishwanathapura@intel.com> X-Mailer: git-send-email 2.21.0.rc0.32.g243a4c7e27 In-Reply-To: <20220921070945.27764-1-niranjana.vishwanathapura@intel.com> References: <20220921070945.27764-1-niranjana.vishwanathapura@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC v4 02/14] drm/i915/vm_bind: Add __i915_sw_fence_await_reservation() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, thomas.hellstrom@intel.com, matthew.auld@intel.com, daniel.vetter@intel.com, christian.koenig@amd.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add function __i915_sw_fence_await_reservation() for asynchronous wait on a dma-resv object with specified dma_resv_usage. This is required for async vma unbind with vm_bind. Signed-off-by: Niranjana Vishwanathapura --- drivers/gpu/drm/i915/i915_sw_fence.c | 25 ++++++++++++++++++------- drivers/gpu/drm/i915/i915_sw_fence.h | 7 ++++++- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index 6fc0d1b89690..0ce8f4efc1ed 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.c +++ b/drivers/gpu/drm/i915/i915_sw_fence.c @@ -569,12 +569,11 @@ int __i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, return ret; } -int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, - struct dma_resv *resv, - const struct dma_fence_ops *exclude, - bool write, - unsigned long timeout, - gfp_t gfp) +int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence, + struct dma_resv *resv, + enum dma_resv_usage usage, + unsigned long timeout, + gfp_t gfp) { struct dma_resv_iter cursor; struct dma_fence *f; @@ -583,7 +582,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, debug_fence_assert(fence); might_sleep_if(gfpflags_allow_blocking(gfp)); - dma_resv_iter_begin(&cursor, resv, dma_resv_usage_rw(write)); + dma_resv_iter_begin(&cursor, resv, usage); dma_resv_for_each_fence_unlocked(&cursor, f) { pending = i915_sw_fence_await_dma_fence(fence, f, timeout, gfp); @@ -598,6 +597,18 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, return ret; } +int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, + struct dma_resv *resv, + const struct dma_fence_ops *exclude, + bool write, + unsigned long timeout, + gfp_t gfp) +{ + return __i915_sw_fence_await_reservation(fence, resv, + dma_resv_usage_rw(write), + timeout, gfp); +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/lib_sw_fence.c" #include "selftests/i915_sw_fence.c" diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h b/drivers/gpu/drm/i915/i915_sw_fence.h index 619fc5a22f0c..3cf4b6e16f35 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.h +++ b/drivers/gpu/drm/i915/i915_sw_fence.h @@ -10,13 +10,13 @@ #define _I915_SW_FENCE_H_ #include +#include #include #include #include /* for NOTIFY_DONE */ #include struct completion; -struct dma_resv; struct i915_sw_fence; enum i915_sw_fence_notify { @@ -89,6 +89,11 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, unsigned long timeout, gfp_t gfp); +int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence, + struct dma_resv *resv, + enum dma_resv_usage usage, + unsigned long timeout, + gfp_t gfp); int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, struct dma_resv *resv, const struct dma_fence_ops *exclude,