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So the device info is passed as a parameter to the macro DDI_BUF_CTL but unused yet. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/icl_dsi.c | 12 +++--- drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++++++++++--------- drivers/gpu/drm/i915/display/intel_display.c | 6 ++- drivers/gpu/drm/i915/display/intel_fdi.c | 14 +++---- drivers/gpu/drm/i915/display/intel_tc.c | 6 +-- drivers/gpu/drm/i915/gvt/display.c | 30 +++++++-------- drivers/gpu/drm/i915/gvt/handlers.c | 17 +++++---- drivers/gpu/drm/i915/i915_reg.h | 6 ++- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 ++--- 9 files changed, 76 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ed4d93942dbd..70098b67149b 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -548,11 +548,11 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) enum port port; for_each_dsi_port(port, intel_dsi->ports) { - tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + tmp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)); tmp |= DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), tmp); - if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) & DDI_BUF_IS_IDLE), 500)) drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", @@ -1400,11 +1400,11 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) gen11_dsi_ungate_clocks(encoder); for_each_dsi_port(port, intel_dsi->ports) { - tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + tmp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)); tmp &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), tmp); - if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) & DDI_BUF_IS_IDLE), 8)) drm_err(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 643832d55c28..aae429bd2e2b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -172,7 +172,7 @@ void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, return; } - if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) & DDI_BUF_IS_IDLE), 8)) drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", port_name(port)); @@ -189,7 +189,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, return; } - ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) & DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10); if (ret) @@ -730,7 +730,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if (!wakeref) return; - tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + tmp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)); if (!(tmp & DDI_BUF_CTL_ENABLE)) goto out; @@ -1397,8 +1397,8 @@ hsw_set_signal_levels(struct intel_encoder *encoder, intel_dp->DP &= ~DDI_BUF_EMP_MASK; intel_dp->DP |= signal_levels; - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), intel_dp->DP); + intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, port)); } static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, @@ -2577,10 +2577,10 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, bool wait = false; u32 val; - val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + val = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)); if (val & DDI_BUF_CTL_ENABLE) { val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), val); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), val); wait = true; } @@ -2909,7 +2909,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), buf_ctl); intel_audio_codec_enable(encoder, crtc_state, conn_state); } @@ -3113,9 +3113,9 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); if (dp_tp_ctl & DP_TP_CTL_ENABLE) { - ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); + ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)); if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { - intel_de_write(dev_priv, DDI_BUF_CTL(port), + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); wait = true; } @@ -3145,8 +3145,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, adlp_tbt_to_dp_alt_switch_wa(encoder); intel_dp->DP |= DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, port), intel_dp->DP); + intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, port)); intel_wait_ddi_buf_active(dev_priv, port); } @@ -3805,13 +3805,15 @@ static struct intel_connector * intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) { struct intel_connector *connector; - enum port port = dig_port->base.port; + struct intel_encoder *encoder = &dig_port->base; + enum port port = encoder->port; + struct drm_i915_private *i915 = to_i915(encoder->base.dev); connector = intel_connector_alloc(); if (!connector) return NULL; - dig_port->dp.output_reg = DDI_BUF_CTL(port); + dig_port->dp.output_reg = DDI_BUF_CTL(i915, port); dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; dig_port->dp.set_link_train = intel_ddi_set_link_train; dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; @@ -4043,12 +4045,13 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) { struct intel_connector *connector; enum port port = dig_port->base.port; + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); connector = intel_connector_alloc(); if (!connector) return NULL; - dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); + dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(dev_priv, port); intel_hdmi_init_connector(dig_port, connector); return connector; @@ -4084,7 +4087,7 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) return max_lanes; if (port == PORT_A || port == PORT_E) { - if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + if (intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_A)) & DDI_A_4_LANES) max_lanes = port == PORT_A ? 4 : 0; else /* Both A and E share 2 lanes */ @@ -4446,11 +4449,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) if (DISPLAY_VER(dev_priv) >= 11) dig_port->saved_port_bits = - intel_de_read(dev_priv, DDI_BUF_CTL(port)) + intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) & DDI_BUF_PORT_REVERSAL; else dig_port->saved_port_bits = - intel_de_read(dev_priv, DDI_BUF_CTL(port)) + intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, port)) & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); if (intel_bios_is_lane_reversal_needed(dev_priv, port)) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index dd008ba8afe3..194a4758ee04 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7880,7 +7880,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) return false; /* DDI E can't be used if DDI A requires 4 lanes */ - if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + if (intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_A)) & DDI_A_4_LANES) return false; if (!dev_priv->display.vbt.int_crt_support) @@ -7966,7 +7966,9 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_crt_init(dev_priv); /* Haswell uses DDI functions to detect digital outputs. */ - found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; + found = intel_de_read(dev_priv, + DDI_BUF_CTL(dev_priv, PORT_A)) & + DDI_INIT_DISPLAY_DETECTED; if (found) intel_ddi_init(dev_priv, PORT_A); diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 7f47e5c85c81..d3d92ac26099 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -818,9 +818,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, * DDI E does not support port reversal, the functionality is * achieved on the PCH side in FDI_RX_CTL, so no need to set the * port reversal bit */ - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E), DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); + intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E)); udelay(600); @@ -864,10 +864,10 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); - temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); + temp = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E)); temp &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E), temp); + intel_de_posting_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E)); /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); @@ -909,9 +909,9 @@ void hsw_fdi_disable(struct intel_encoder *encoder) val &= ~FDI_RX_ENABLE; intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); - val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); + val = intel_de_read(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E)); val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val); + intel_de_write(dev_priv, DDI_BUF_CTL(dev_priv, PORT_E), val); intel_wait_ddi_buf_idle(dev_priv, PORT_E); diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index e5af955b5600..8baee1f19d89 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -410,12 +410,12 @@ static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port, enum port port = dig_port->base.port; u32 val; - val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); + val = intel_uncore_read(uncore, DDI_BUF_CTL(i915, port)); if (take) val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; else val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP; - intel_uncore_write(uncore, DDI_BUF_CTL(port), val); + intel_uncore_write(uncore, DDI_BUF_CTL(i915, port), val); return true; } @@ -455,7 +455,7 @@ static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port) enum port port = dig_port->base.port; u32 val; - val = intel_uncore_read(uncore, DDI_BUF_CTL(port)); + val = intel_uncore_read(uncore, DDI_BUF_CTL(i915, port)); return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP; } diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index c7722c818b4d..5e3cd306c41d 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -213,10 +213,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) PORT_PLL_REF_SEL | PORT_PLL_LOCK | PORT_PLL_ENABLE); - vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &= + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, port)) &= ~(DDI_INIT_DISPLAY_DETECTED | DDI_BUF_CTL_ENABLE); - vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, port)) |= DDI_BUF_IS_IDLE; } vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK); @@ -276,9 +276,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | PORT_PLL_REF_SEL | PORT_PLL_LOCK | PORT_PLL_ENABLE); - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_A)) |= (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_A)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | @@ -305,9 +305,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | PORT_PLL_REF_SEL | PORT_PLL_LOCK | PORT_PLL_ENABLE); - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) |= DDI_BUF_CTL_ENABLE; - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | @@ -335,9 +335,9 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE | PORT_PLL_REF_SEL | PORT_PLL_LOCK | PORT_PLL_ENABLE); - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) |= DDI_BUF_CTL_ENABLE; - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | @@ -416,8 +416,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |= PORT_CLK_SEL_LCPLL_810; } - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE; - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) |= DDI_BUF_CTL_ENABLE; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_B)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT; } @@ -442,8 +442,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |= PORT_CLK_SEL_LCPLL_810; } - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE; - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) |= DDI_BUF_CTL_ENABLE; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_C)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED; } @@ -468,8 +468,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |= PORT_CLK_SEL_LCPLL_810; } - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE; - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_D)) |= DDI_BUF_CTL_ENABLE; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_D)) &= ~DDI_BUF_IS_IDLE; vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; } @@ -488,7 +488,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) else vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT; - vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; + vgpu_vreg_t(vgpu, DDI_BUF_CTL(dev_priv, PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; } /* Clear host CRT status, so guest couldn't detect this host CRT. */ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index daac2050d77d..15393c861721 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -787,13 +787,15 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu, static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { + struct drm_i915_private *i915 = vgpu->gvt->gt->i915; + write_vreg(vgpu, offset, p_data, bytes); if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; } else { vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; - if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) + if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(i915, PORT_E))) vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) &= ~DP_TP_STATUS_AUTOTRAIN_DONE; } @@ -812,7 +814,8 @@ static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, static int fdi_auto_training_started(struct intel_vgpu *vgpu) { - u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); + struct drm_i915_private *i915 = vgpu->gvt->gt->i915; + u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(i915, PORT_E)); u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); @@ -2333,11 +2336,11 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, dp_aux_ch_ctl_mmio_write); - MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); - MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); - MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); - MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); - MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); + MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); + MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); + MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); + MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); + MMIO_DH(DDI_BUF_CTL(dev_priv, PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5003a5ffbc6a..67f3b17b2360 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6936,7 +6936,11 @@ enum skl_power_gate { /* DDI Buffer Control */ #define _DDI_BUF_CTL_A 0x64000 #define _DDI_BUF_CTL_B 0x64100 -#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) +#define DDI_BUF_CTL(i915, port) ({ \ + (void)i915; /* Suppress unused variable warning */ \ + _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B); \ + }) + #define DDI_BUF_CTL_ENABLE (1 << 31) #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) #define DDI_BUF_EMP_MASK (0xf << 24) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 8279dc580a3e..b55bdc2cdd84 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -503,11 +503,11 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(SBI_CTL_STAT); MMIO_D(PIXCLK_GATE); MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4); - MMIO_D(DDI_BUF_CTL(PORT_A)); - MMIO_D(DDI_BUF_CTL(PORT_B)); - MMIO_D(DDI_BUF_CTL(PORT_C)); - MMIO_D(DDI_BUF_CTL(PORT_D)); - MMIO_D(DDI_BUF_CTL(PORT_E)); + MMIO_D(DDI_BUF_CTL(dev_priv, PORT_A)); + MMIO_D(DDI_BUF_CTL(dev_priv, PORT_B)); + MMIO_D(DDI_BUF_CTL(dev_priv, PORT_C)); + MMIO_D(DDI_BUF_CTL(dev_priv, PORT_D)); + MMIO_D(DDI_BUF_CTL(dev_priv, PORT_E)); MMIO_D(DP_TP_CTL(PORT_A)); MMIO_D(DP_TP_CTL(PORT_B)); MMIO_D(DP_TP_CTL(PORT_C));