@@ -130,6 +130,42 @@
[PIPE_D] = TGL_CURSOR_D_OFFSET, \
}
+#define GEN9_DDI_INDEX \
+ .display.ddi_index = { \
+ [PORT_A] = 0, \
+ [PORT_B] = 1, \
+ [PORT_C] = 2, \
+ [PORT_D] = 3, \
+ [PORT_E] = 4, \
+ [PORT_F] = 5, \
+ }
+
+#define GEN12_DDI_INDEX \
+ .display.ddi_index = { \
+ [PORT_A] = 0, \
+ [PORT_B] = 1, \
+ [PORT_C] = 2, \
+ [PORT_TC1] = 3, \
+ [PORT_TC2] = 4, \
+ [PORT_TC3] = 5, \
+ [PORT_TC4] = 6, \
+ [PORT_TC5] = 7, \
+ [PORT_TC6] = 8, \
+ }
+
+#define XE_LPD_DDI_INDEX \
+ .display.ddi_index = { \
+ [PORT_A] = 0, \
+ [PORT_B] = 1, \
+ [PORT_C] = 2, \
+ [PORT_TC1] = 3, \
+ [PORT_TC2] = 4, \
+ [PORT_TC3] = 5, \
+ [PORT_TC4] = 6, \
+ [PORT_D_XELPD] = 7, \
+ [PORT_E_XELPD] = 8, \
+ }
+
#define I9XX_COLORS \
.display.color = { .gamma_lut_size = 256 }
#define I965_COLORS \
@@ -664,7 +700,8 @@ static const struct intel_device_info chv_info = {
.display.has_psr = 1, \
.display.has_psr_hw_tracking = 1, \
.display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
- .display.dbuf.slice_mask = BIT(DBUF_S1)
+ .display.dbuf.slice_mask = BIT(DBUF_S1), \
+ GEN9_DDI_INDEX
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -732,7 +769,8 @@ static const struct intel_device_info skl_gt4_info = {
IVB_CURSOR_OFFSETS, \
IVB_COLORS, \
GEN9_DEFAULT_PAGE_SIZES, \
- GEN_DEFAULT_REGIONS
+ GEN_DEFAULT_REGIONS, \
+ GEN9_DDI_INDEX
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
@@ -886,6 +924,7 @@ static const struct intel_device_info jsl_info = {
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
TGL_CURSOR_OFFSETS, \
+ GEN12_DDI_INDEX, \
.has_global_mocs = 1, \
.has_pxp = 1, \
.display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
@@ -983,7 +1022,8 @@ static const struct intel_device_info adl_s_info = {
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
}, \
- TGL_CURSOR_OFFSETS
+ TGL_CURSOR_OFFSETS, \
+ XE_LPD_DDI_INDEX
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
@@ -292,6 +292,7 @@ struct intel_device_info {
u32 pipe_offsets[I915_MAX_TRANSCODERS];
u32 trans_offsets[I915_MAX_TRANSCODERS];
u32 cursor_offsets[I915_MAX_PIPES];
+ u32 ddi_index[I915_MAX_PORTS];
struct {
u32 degamma_lut_size;
Prior to display version 12, platforms had DDI ports A,B,C,D,E,F represented by enums PORT_A,PORT_B...PORT_F. The DDI register offsets of the ports was in the same order as the ports. So the port enums were directly used as index to calculate the register offset of the ports. Starting in display version 12, TypeC ports were introduced in the platforms. These were defined as new enums PORT_TC1,PORT_TC2... The later generation platforms had DDI register offests of TypeC and non-TypeC ports interleaved and the existing port enums didn't match the order of the DDI register offests. So the enums could no more be used as index to calculate the register offest. This led to the creation of new platform specific enums for the ports like PORT_D_XELPD, PORT_E_XELPD to match the index of the ports in those platforms and additional code to handle the special enums. So we want to make the port enums not tied to DDI register offset and use the index from somewhere else to calculate the register offsets. The index of the DDI ports in the platform is now defined as part of device info. This patch just adds the indices to the device info. Later patches in the series use that index for offset calculation. Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 46 ++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_device_info.h | 1 + 2 files changed, 44 insertions(+), 3 deletions(-)