| Message ID | 20221003072011.72408-1-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4] drm/i915/psr: Fix PSR_IMR/IIR field handling | expand |
On Mon, 2022-10-03 at 10:20 +0300, Jouni Högander wrote: > Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift for > bits in PSR_IMR/IIR registers: > > /* > * gen12+ has registers relative to transcoder and one per transcoder > * using the same bit definition: handle it as TRANSCODER_EDP to force > * 0 shift in bit definition > */ > > At the time of writing the code assumption "TRANSCODER_EDP == 0" was made. > This is not the case and all fields in PSR_IMR and PSR_IIR are shifted > incorrectly if DISPLAY_VER >= 12. > > Fix this by adding separate register field defines for >=12 and add bit > getter functions to keep code readability. > > v4: > - Remove EDP from TGL definitions (José) > - Use REG_BIT and REG_GENMASK (José) > v3: > - Add separate register field defines (José) > - Add bit getter functions (José) > v2: > - Improve commit message (José) Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Mika Kahola <mika.kahola@intel.com> > > Fixes: 8241cfbe67f4 ("drm/i915/tgl: Access the right register when handling PSR interruptions") > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 78 ++++++++++++++---------- > drivers/gpu/drm/i915/i915_reg.h | 16 +++-- > 2 files changed, 59 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 9def8d9fade6..d4cce627d7a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -116,34 +116,56 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp) > } > } > > +static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : > + EDP_PSR_ERROR(intel_dp->psr.transcoder); > +} > + > +static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : > + EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); > +} > + > +static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : > + EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); > +} > + > +static u32 psr_irq_mask_get(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : > + EDP_PSR_MASK(intel_dp->psr.transcoder); > +} > + > static void psr_irq_control(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - enum transcoder trans_shift; > i915_reg_t imr_reg; > u32 mask, val; > > - /* > - * gen12+ has registers relative to transcoder and one per transcoder > - * using the same bit definition: handle it as TRANSCODER_EDP to force > - * 0 shift in bit definition > - */ > - if (DISPLAY_VER(dev_priv) >= 12) { > - trans_shift = 0; > + if (DISPLAY_VER(dev_priv) >= 12) > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); > - } else { > - trans_shift = intel_dp->psr.transcoder; > + else > imr_reg = EDP_PSR_IMR; > - } > > - mask = EDP_PSR_ERROR(trans_shift); > + mask = psr_irq_psr_error_bit_get(intel_dp); > if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) > - mask |= EDP_PSR_POST_EXIT(trans_shift) | > - EDP_PSR_PRE_ENTRY(trans_shift); > + mask |= psr_irq_post_exit_bit_get(intel_dp) | > + psr_irq_pre_entry_bit_get(intel_dp); > > - /* Warning: it is masking/setting reserved bits too */ > val = intel_de_read(dev_priv, imr_reg); > - val &= ~EDP_PSR_TRANS_MASK(trans_shift); > + val &= ~psr_irq_mask_get(intel_dp); > val |= ~mask; > intel_de_write(dev_priv, imr_reg, val); > } > @@ -191,25 +213,21 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) > enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > ktime_t time_ns = ktime_get(); > - enum transcoder trans_shift; > i915_reg_t imr_reg; > > - if (DISPLAY_VER(dev_priv) >= 12) { > - trans_shift = 0; > + if (DISPLAY_VER(dev_priv) >= 12) > imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); > - } else { > - trans_shift = intel_dp->psr.transcoder; > + else > imr_reg = EDP_PSR_IMR; > - } > > - if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { > + if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { > intel_dp->psr.last_entry_attempt = time_ns; > drm_dbg_kms(&dev_priv->drm, > "[transcoder %s] PSR entry attempt in 2 vblanks\n", > transcoder_name(cpu_transcoder)); > } > > - if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { > + if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { > intel_dp->psr.last_exit = time_ns; > drm_dbg_kms(&dev_priv->drm, > "[transcoder %s] PSR exit completed\n", > @@ -226,7 +244,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) > } > } > > - if (psr_iir & EDP_PSR_ERROR(trans_shift)) { > + if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { > u32 val; > > drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", > @@ -243,7 +261,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) > * or unset irq_aux_error. > */ > val = intel_de_read(dev_priv, imr_reg); > - val |= EDP_PSR_ERROR(trans_shift); > + val |= psr_irq_psr_error_bit_get(intel_dp); > intel_de_write(dev_priv, imr_reg, val); > > schedule_work(&intel_dp->psr.work); > @@ -1194,14 +1212,12 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp) > * first time that PSR HW tries to activate so lets keep PSR disabled > * to avoid any rendering problems. > */ > - if (DISPLAY_VER(dev_priv) >= 12) { > + if (DISPLAY_VER(dev_priv) >= 12) > val = intel_de_read(dev_priv, > TRANS_PSR_IIR(intel_dp->psr.transcoder)); > - val &= EDP_PSR_ERROR(0); > - } else { > + else > val = intel_de_read(dev_priv, EDP_PSR_IIR); > - val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); > - } > + val &= psr_irq_psr_error_bit_get(intel_dp); > if (val) { > intel_dp->psr.sink_not_reliable = true; > drm_dbg_kms(&dev_priv->drm, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2126e441199d..a175fb1900fe 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2168,10 +2168,18 @@ > #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) > #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ > 0 : ((trans) - TRANSCODER_A + 1) * 8) > -#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)) > -#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)) > -#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)) > -#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)) > +#define TGL_PSR_MASK REG_GENMASK(2, 0) > +#define TGL_PSR_ERROR REG_BIT(2) > +#define TGL_PSR_POST_EXIT REG_BIT(1) > +#define TGL_PSR_PRE_ENTRY REG_BIT(0) > +#define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ > + _EDP_PSR_TRANS_SHIFT(trans)) > +#define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ > + _EDP_PSR_TRANS_SHIFT(trans)) > +#define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ > + _EDP_PSR_TRANS_SHIFT(trans)) > +#define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ > + _EDP_PSR_TRANS_SHIFT(trans)) > > #define _SRD_AUX_DATA_A 0x60814 > #define _SRD_AUX_DATA_EDP 0x6f814
On Mon, 2022-10-03 at 09:30 +0000, Patchwork wrote:
Patch Details
Series: drm/i915/psr: Fix PSR_IMR/IIR field handling (rev4)
URL: https://patchwork.freedesktop.org/series/108811/
State: success
Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/index.html
CI Bug Log - changes from CI_DRM_12204_full -> Patchwork_108811v4_full
Summary
SUCCESS
No regressions found.
Pushed to drm-intel-next, thanks for the patch.
Participating hosts (9 -> 9)
No changes in participating hosts
Known issues
Here are the changes found in Patchwork_108811v4_full that come from known issues:
CI changes
Possible fixes
* boot:
* shard-apl: (PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl6/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl6/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl6/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html>, FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl3/boot.html>) (i915#4386<https://gitlab.freedesktop.org/drm/intel/issues/4386>) -> (PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl8/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl7/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl6/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl6/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl6/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl6/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl1/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl2/boot.html>, PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl1/boot.html>)
IGT changes
Issues hit
* igt@gem_create@create-massive:
* shard-apl: NOTRUN -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@gem_create@create-massive.html> (i915#4991<https://gitlab.freedesktop.org/drm/intel/issues/4991>)
* igt@gem_ctx_persistence@legacy-engines-cleanup:
* shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-snb2/igt@gem_ctx_persistence@legacy-engines-cleanup.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#1099<https://gitlab.freedesktop.org/drm/intel/issues/1099>)
* igt@gem_eio@kms:
* shard-tglb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb3/igt@gem_eio@kms.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-tglb1/igt@gem_eio@kms.html> (i915#5784<https://gitlab.freedesktop.org/drm/intel/issues/5784>)
* igt@gem_exec_balancer@parallel-bb-first:
* shard-iclb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html> -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html> (i915#4525<https://gitlab.freedesktop.org/drm/intel/issues/4525>)
* igt@gem_exec_fair@basic-pace-share@rcs0:
* shard-glk: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html> (i915#2842<https://gitlab.freedesktop.org/drm/intel/issues/2842>)
* igt@gem_lmem_swapping@parallel-multi:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@gem_lmem_swapping@parallel-multi.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#4613<https://gitlab.freedesktop.org/drm/intel/issues/4613>)
* igt@gem_softpin@evict-single-offset:
* shard-apl: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@gem_softpin@evict-single-offset.html> (i915#4171<https://gitlab.freedesktop.org/drm/intel/issues/4171>)
* igt@i915_suspend@basic-s3-without-i915:
* shard-iclb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb5/igt@i915_suspend@basic-s3-without-i915.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb3/igt@i915_suspend@basic-s3-without-i915.html> (i915#5982<https://gitlab.freedesktop.org/drm/intel/issues/5982>)
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#3886<https://gitlab.freedesktop.org/drm/intel/issues/3886>) +1 similar issue
* igt@kms_chamelium@vga-frame-dump:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@kms_chamelium@vga-frame-dump.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / fdo#111827<https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +5 similar issues
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html> (i915#2587<https://gitlab.freedesktop.org/drm/intel/issues/2587> / i915#2672<https://gitlab.freedesktop.org/drm/intel/issues/2672>)
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-default-mode:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-default-mode.html> (i915#2672<https://gitlab.freedesktop.org/drm/intel/issues/2672>) +4 similar issues
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
* shard-iclb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html> (i915#6375<https://gitlab.freedesktop.org/drm/intel/issues/6375>)
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-cpu:
* shard-snb: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-snb2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-cpu.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +37 similar issues
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +60 similar issues
* igt@kms_psr@psr2_primary_mmap_cpu:
* shard-iclb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html> -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html> (fdo#109441<https://bugs.freedesktop.org/show_bug.cgi?id=109441>) +1 similar issue
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
* shard-tglb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb8/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html> -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-tglb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html> (i915#5519<https://gitlab.freedesktop.org/drm/intel/issues/5519>)
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
* shard-apl: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl2/igt@kms_vblank@pipe-b-ts-continuation-suspend.html> (i915#180<https://gitlab.freedesktop.org/drm/intel/issues/180>) +1 similar issue
* igt@kms_vblank@pipe-d-wait-idle:
* shard-apl: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@kms_vblank@pipe-d-wait-idle.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#533<https://gitlab.freedesktop.org/drm/intel/issues/533>)
Possible fixes
* igt@gem_exec_fair@basic-none-share@rcs0:
* shard-glk: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html> (i915#2842<https://gitlab.freedesktop.org/drm/intel/issues/2842>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html> +1 similar issue
* igt@gen9_exec_parse@bb-large:
* shard-apl: TIMEOUT<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl2/igt@gen9_exec_parse@bb-large.html> (i915#4639<https://gitlab.freedesktop.org/drm/intel/issues/4639>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl7/igt@gen9_exec_parse@bb-large.html>
* igt@i915_selftest@live@hangcheck:
* shard-snb: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-snb4/igt@i915_selftest@live@hangcheck.html> (i915#6992<https://gitlab.freedesktop.org/drm/intel/issues/6992>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-snb2/igt@i915_selftest@live@hangcheck.html>
* igt@i915_suspend@forcewake:
* shard-apl: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-apl1/igt@i915_suspend@forcewake.html> (i915#180<https://gitlab.freedesktop.org/drm/intel/issues/180>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-apl3/igt@i915_suspend@forcewake.html> +1 similar issue
* igt@kms_addfb_basic@legacy-format:
* shard-tglb: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb3/igt@kms_addfb_basic@legacy-format.html> (i915#6987<https://gitlab.freedesktop.org/drm/intel/issues/6987>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-tglb8/igt@kms_addfb_basic@legacy-format.html>
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
* shard-glk: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html> (i915#2346<https://gitlab.freedesktop.org/drm/intel/issues/2346>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html>
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html> (i915#5235<https://gitlab.freedesktop.org/drm/intel/issues/5235>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html> +2 similar issues
* igt@kms_psr2_su@page_flip-xrgb8888:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb3/igt@kms_psr2_su@page_flip-xrgb8888.html> (fdo#109642<https://bugs.freedesktop.org/show_bug.cgi?id=109642> / fdo#111068<https://bugs.freedesktop.org/show_bug.cgi?id=111068> / i915#658<https://gitlab.freedesktop.org/drm/intel/issues/658>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html>
* igt@kms_psr@psr2_basic:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb8/igt@kms_psr@psr2_basic.html> (fdo#109441<https://bugs.freedesktop.org/show_bug.cgi?id=109441>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb2/igt@kms_psr@psr2_basic.html>
* igt@perf@polling-parameterized:
* shard-tglb: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-tglb7/igt@perf@polling-parameterized.html> (i915#5639<https://gitlab.freedesktop.org/drm/intel/issues/5639>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-tglb7/igt@perf@polling-parameterized.html>
Warnings
* igt@i915_pm_dc@dc3co-vpb-simulation:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html> (i915#588<https://gitlab.freedesktop.org/drm/intel/issues/588>) -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html> (i915#658<https://gitlab.freedesktop.org/drm/intel/issues/658>)
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html> (i915#658<https://gitlab.freedesktop.org/drm/intel/issues/658>) -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html> (i915#2920<https://gitlab.freedesktop.org/drm/intel/issues/2920>)
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html> (fdo#111068<https://bugs.freedesktop.org/show_bug.cgi?id=111068> / i915#658<https://gitlab.freedesktop.org/drm/intel/issues/658>) -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html> (i915#2920<https://gitlab.freedesktop.org/drm/intel/issues/2920>)
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html> (i915#2920<https://gitlab.freedesktop.org/drm/intel/issues/2920>) -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html> (i915#658<https://gitlab.freedesktop.org/drm/intel/issues/658>)
* igt@kms_psr2_su@page_flip-p010:
* shard-iclb: SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12204/shard-iclb4/igt@kms_psr2_su@page_flip-p010.html> (fdo#109642<https://bugs.freedesktop.org/show_bug.cgi?id=109642> / fdo#111068<https://bugs.freedesktop.org/show_bug.cgi?id=111068> / i915#658<https://gitlab.freedesktop.org/drm/intel/issues/658>) -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html> (i915#5939<https://gitlab.freedesktop.org/drm/intel/issues/5939>)
Piglit changes
Issues hit
* spec@ext_shader_framebuffer_fetch@execution@mrt-gles2:
* pig-kbl-iris: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108811v4/pig-kbl-iris/spec@ext_shader_framebuffer_fetch@execution@mrt-gles2.html> (i915#5603<https://gitlab.freedesktop.org/drm/intel/issues/5603>)
Build changes
* Linux: CI_DRM_12204 -> Patchwork_108811v4
CI-20190529: 20190529
CI_DRM_12204: fd2f9b9a4178e667adad268a662eb8a9c0ddc8f8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6670: d618e9865fe5cbaf511ca43503abad442605d0a5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108811v4: fd2f9b9a4178e667adad268a662eb8a9c0ddc8f8 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9def8d9fade6..d4cce627d7a8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -116,34 +116,56 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp) } } +static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR : + EDP_PSR_ERROR(intel_dp->psr.transcoder); +} + +static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT : + EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); +} + +static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY : + EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); +} + +static u32 psr_irq_mask_get(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK : + EDP_PSR_MASK(intel_dp->psr.transcoder); +} + static void psr_irq_control(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - enum transcoder trans_shift; i915_reg_t imr_reg; u32 mask, val; - /* - * gen12+ has registers relative to transcoder and one per transcoder - * using the same bit definition: handle it as TRANSCODER_EDP to force - * 0 shift in bit definition - */ - if (DISPLAY_VER(dev_priv) >= 12) { - trans_shift = 0; + if (DISPLAY_VER(dev_priv) >= 12) imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); - } else { - trans_shift = intel_dp->psr.transcoder; + else imr_reg = EDP_PSR_IMR; - } - mask = EDP_PSR_ERROR(trans_shift); + mask = psr_irq_psr_error_bit_get(intel_dp); if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) - mask |= EDP_PSR_POST_EXIT(trans_shift) | - EDP_PSR_PRE_ENTRY(trans_shift); + mask |= psr_irq_post_exit_bit_get(intel_dp) | + psr_irq_pre_entry_bit_get(intel_dp); - /* Warning: it is masking/setting reserved bits too */ val = intel_de_read(dev_priv, imr_reg); - val &= ~EDP_PSR_TRANS_MASK(trans_shift); + val &= ~psr_irq_mask_get(intel_dp); val |= ~mask; intel_de_write(dev_priv, imr_reg, val); } @@ -191,25 +213,21 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) enum transcoder cpu_transcoder = intel_dp->psr.transcoder; struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); ktime_t time_ns = ktime_get(); - enum transcoder trans_shift; i915_reg_t imr_reg; - if (DISPLAY_VER(dev_priv) >= 12) { - trans_shift = 0; + if (DISPLAY_VER(dev_priv) >= 12) imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); - } else { - trans_shift = intel_dp->psr.transcoder; + else imr_reg = EDP_PSR_IMR; - } - if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { + if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { intel_dp->psr.last_entry_attempt = time_ns; drm_dbg_kms(&dev_priv->drm, "[transcoder %s] PSR entry attempt in 2 vblanks\n", transcoder_name(cpu_transcoder)); } - if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { + if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { intel_dp->psr.last_exit = time_ns; drm_dbg_kms(&dev_priv->drm, "[transcoder %s] PSR exit completed\n", @@ -226,7 +244,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) } } - if (psr_iir & EDP_PSR_ERROR(trans_shift)) { + if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { u32 val; drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", @@ -243,7 +261,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) * or unset irq_aux_error. */ val = intel_de_read(dev_priv, imr_reg); - val |= EDP_PSR_ERROR(trans_shift); + val |= psr_irq_psr_error_bit_get(intel_dp); intel_de_write(dev_priv, imr_reg, val); schedule_work(&intel_dp->psr.work); @@ -1194,14 +1212,12 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp) * first time that PSR HW tries to activate so lets keep PSR disabled * to avoid any rendering problems. */ - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(dev_priv) >= 12) val = intel_de_read(dev_priv, TRANS_PSR_IIR(intel_dp->psr.transcoder)); - val &= EDP_PSR_ERROR(0); - } else { + else val = intel_de_read(dev_priv, EDP_PSR_IIR); - val &= EDP_PSR_ERROR(intel_dp->psr.transcoder); - } + val &= psr_irq_psr_error_bit_get(intel_dp); if (val) { intel_dp->psr.sink_not_reliable = true; drm_dbg_kms(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2126e441199d..a175fb1900fe 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2168,10 +2168,18 @@ #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 0 : ((trans) - TRANSCODER_A + 1) * 8) -#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)) -#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)) -#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)) -#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)) +#define TGL_PSR_MASK REG_GENMASK(2, 0) +#define TGL_PSR_ERROR REG_BIT(2) +#define TGL_PSR_POST_EXIT REG_BIT(1) +#define TGL_PSR_PRE_ENTRY REG_BIT(0) +#define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ + _EDP_PSR_TRANS_SHIFT(trans)) +#define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ + _EDP_PSR_TRANS_SHIFT(trans)) +#define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ + _EDP_PSR_TRANS_SHIFT(trans)) +#define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ + _EDP_PSR_TRANS_SHIFT(trans)) #define _SRD_AUX_DATA_A 0x60814 #define _SRD_AUX_DATA_EDP 0x6f814
Current PSR code is supposed to use TRANSCODER_EDP to force 0 shift for bits in PSR_IMR/IIR registers: /* * gen12+ has registers relative to transcoder and one per transcoder * using the same bit definition: handle it as TRANSCODER_EDP to force * 0 shift in bit definition */ At the time of writing the code assumption "TRANSCODER_EDP == 0" was made. This is not the case and all fields in PSR_IMR and PSR_IIR are shifted incorrectly if DISPLAY_VER >= 12. Fix this by adding separate register field defines for >=12 and add bit getter functions to keep code readability. v4: - Remove EDP from TGL definitions (José) - Use REG_BIT and REG_GENMASK (José) v3: - Add separate register field defines (José) - Add bit getter functions (José) v2: - Improve commit message (José) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Fixes: 8241cfbe67f4 ("drm/i915/tgl: Access the right register when handling PSR interruptions") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 78 ++++++++++++++---------- drivers/gpu/drm/i915/i915_reg.h | 16 +++-- 2 files changed, 59 insertions(+), 35 deletions(-)