| Message ID | 20221005154159.18750-2-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] drm/i915: Extract intel_mmio_bar() | expand |
On Wed, 5 Oct 2022 at 16:42, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > We use all kinds of weird names for our base address registers. > Take the names from the spec and stick to them to avoid confusing > everyone. > > The only exceptions are IOBAR and LMEMBAR since naming them > IOBAR_BAR and LMEMBAR_BAR looks too funny, and yet I think > that adding the _BAR to GTTMMADR & co. (which don't have one > in the spec name) does make it more clear what they are. > And IOBAR vs. GTTMMADR_BAR also looks a bit too inconsistent > for my taste. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > .../gpu/drm/i915/display/intel_lpe_audio.c | 4 ++-- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 +++++----- > drivers/gpu/drm/i915/gvt/cfg_space.c | 2 +- > drivers/gpu/drm/i915/intel_pci_config.h | 23 +++++++++++++------ > 4 files changed, 25 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c > index dca6003ccac8..389ccdc46a1e 100644 > --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c > +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c > @@ -101,9 +101,9 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) > rsc[0].flags = IORESOURCE_IRQ; > rsc[0].name = "hdmi-lpe-audio-irq"; > > - rsc[1].start = pci_resource_start(pdev, GTTMMADR_BAR) + > + rsc[1].start = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + > I915_HDMI_LPE_AUDIO_BASE; > - rsc[1].end = pci_resource_start(pdev, GTTMMADR_BAR) + > + rsc[1].end = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + > I915_HDMI_LPE_AUDIO_BASE + I915_HDMI_LPE_AUDIO_SIZE - 1; > rsc[1].flags = IORESOURCE_MEM; > rsc[1].name = "hdmi-lpe-audio-mmio"; > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > index b31fe0fb013f..668131c25da7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > @@ -871,8 +871,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) > u32 pte_flags; > int ret; > > - GEM_WARN_ON(pci_resource_len(pdev, GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); > - phys_addr = pci_resource_start(pdev, GTTMMADR_BAR) + gen6_gttadr_offset(i915); > + GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); > + phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915); > > /* > * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range > @@ -932,10 +932,10 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) > u16 snb_gmch_ctl; > > if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) { > - if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) > + if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR)) > return -ENXIO; > > - ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); > + ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR); > ggtt->mappable_end = resource_size(&ggtt->gmadr); > } > > @@ -1089,10 +1089,10 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) > unsigned int size; > u16 snb_gmch_ctl; > > - if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) > + if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR)) > return -ENXIO; > > - ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); > + ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR); > ggtt->mappable_end = resource_size(&ggtt->gmadr); > > /* > diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c > index eef3bba8a41b..19a663f6504f 100644 > --- a/drivers/gpu/drm/i915/gvt/cfg_space.c > +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c > @@ -356,7 +356,7 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, > vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = > pci_resource_len(pdev, GTTMMADR_BAR); > vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = > - pci_resource_len(pdev, GTT_APERTURE_BAR); > + pci_resource_len(pdev, GMADR_BAR); Hmm, where is that defined? Typo?
On Wed, Oct 05, 2022 at 05:02:58PM +0100, Matthew Auld wrote: > On Wed, 5 Oct 2022 at 16:42, Ville Syrjala > <ville.syrjala@linux.intel.com> wrote: > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > We use all kinds of weird names for our base address registers. > > Take the names from the spec and stick to them to avoid confusing > > everyone. > > > > The only exceptions are IOBAR and LMEMBAR since naming them > > IOBAR_BAR and LMEMBAR_BAR looks too funny, and yet I think > > that adding the _BAR to GTTMMADR & co. (which don't have one > > in the spec name) does make it more clear what they are. > > And IOBAR vs. GTTMMADR_BAR also looks a bit too inconsistent > > for my taste. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > .../gpu/drm/i915/display/intel_lpe_audio.c | 4 ++-- > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 12 +++++----- > > drivers/gpu/drm/i915/gvt/cfg_space.c | 2 +- > > drivers/gpu/drm/i915/intel_pci_config.h | 23 +++++++++++++------ > > 4 files changed, 25 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c > > index dca6003ccac8..389ccdc46a1e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c > > +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c > > @@ -101,9 +101,9 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) > > rsc[0].flags = IORESOURCE_IRQ; > > rsc[0].name = "hdmi-lpe-audio-irq"; > > > > - rsc[1].start = pci_resource_start(pdev, GTTMMADR_BAR) + > > + rsc[1].start = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + > > I915_HDMI_LPE_AUDIO_BASE; > > - rsc[1].end = pci_resource_start(pdev, GTTMMADR_BAR) + > > + rsc[1].end = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + > > I915_HDMI_LPE_AUDIO_BASE + I915_HDMI_LPE_AUDIO_SIZE - 1; > > rsc[1].flags = IORESOURCE_MEM; > > rsc[1].name = "hdmi-lpe-audio-mmio"; > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c > > index b31fe0fb013f..668131c25da7 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > > @@ -871,8 +871,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) > > u32 pte_flags; > > int ret; > > > > - GEM_WARN_ON(pci_resource_len(pdev, GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); > > - phys_addr = pci_resource_start(pdev, GTTMMADR_BAR) + gen6_gttadr_offset(i915); > > + GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); > > + phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915); > > > > /* > > * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range > > @@ -932,10 +932,10 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) > > u16 snb_gmch_ctl; > > > > if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) { > > - if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) > > + if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR)) > > return -ENXIO; > > > > - ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); > > + ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR); > > ggtt->mappable_end = resource_size(&ggtt->gmadr); > > } > > > > @@ -1089,10 +1089,10 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) > > unsigned int size; > > u16 snb_gmch_ctl; > > > > - if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) > > + if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR)) > > return -ENXIO; > > > > - ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); > > + ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR); > > ggtt->mappable_end = resource_size(&ggtt->gmadr); > > > > /* > > diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c > > index eef3bba8a41b..19a663f6504f 100644 > > --- a/drivers/gpu/drm/i915/gvt/cfg_space.c > > +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c > > @@ -356,7 +356,7 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, > > vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = > > pci_resource_len(pdev, GTTMMADR_BAR); > > vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = > > - pci_resource_len(pdev, GTT_APERTURE_BAR); > > + pci_resource_len(pdev, GMADR_BAR); > > Hmm, where is that defined? Typo? Was supposed to be GEN4_GMADR_BAR. Apparently I have lost gvt from my .config once again...
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Ville-Syrjala/drm-i915-Extract-intel_mmio_bar/20221005-234315
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-rhel-8.3-syz
compiler: gcc-11 (Debian 11.3.0-5) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/1c3b5abb99542ae6b9dbe1b15a7288364c4f2f5f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-Extract-intel_mmio_bar/20221005-234315
git checkout 1c3b5abb99542ae6b9dbe1b15a7288364c4f2f5f
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/display/intel_opregion.h:29,
from drivers/gpu/drm/i915/display/intel_display_core.h:26,
from drivers/gpu/drm/i915/i915_drv.h:40,
from drivers/gpu/drm/i915/gvt/cfg_space.c:34:
drivers/gpu/drm/i915/gvt/cfg_space.c: In function 'intel_vgpu_init_cfg_space':
>> drivers/gpu/drm/i915/gvt/cfg_space.c:357:40: error: 'GTTMMADR_BAR' undeclared (first use in this function); did you mean 'GEN2_MMADR_BAR'?
357 | pci_resource_len(pdev, GTTMMADR_BAR);
| ^~~~~~~~~~~~
include/linux/pci.h:1941:59: note: in definition of macro 'pci_resource_end'
1941 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
| ^~~
drivers/gpu/drm/i915/gvt/cfg_space.c:357:17: note: in expansion of macro 'pci_resource_len'
357 | pci_resource_len(pdev, GTTMMADR_BAR);
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/cfg_space.c:357:40: note: each undeclared identifier is reported only once for each function it appears in
357 | pci_resource_len(pdev, GTTMMADR_BAR);
| ^~~~~~~~~~~~
include/linux/pci.h:1941:59: note: in definition of macro 'pci_resource_end'
1941 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
| ^~~
drivers/gpu/drm/i915/gvt/cfg_space.c:357:17: note: in expansion of macro 'pci_resource_len'
357 | pci_resource_len(pdev, GTTMMADR_BAR);
| ^~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/cfg_space.c:359:40: error: 'GMADR_BAR' undeclared (first use in this function)
359 | pci_resource_len(pdev, GMADR_BAR);
| ^~~~~~~~~
include/linux/pci.h:1941:59: note: in definition of macro 'pci_resource_end'
1941 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
| ^~~
drivers/gpu/drm/i915/gvt/cfg_space.c:359:17: note: in expansion of macro 'pci_resource_len'
359 | pci_resource_len(pdev, GMADR_BAR);
| ^~~~~~~~~~~~~~~~
vim +357 drivers/gpu/drm/i915/gvt/cfg_space.c
536fc234074b09 Changbin Du 2017-01-13 311
536fc234074b09 Changbin Du 2017-01-13 312 /**
536fc234074b09 Changbin Du 2017-01-13 313 * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU
536fc234074b09 Changbin Du 2017-01-13 314 *
536fc234074b09 Changbin Du 2017-01-13 315 * @vgpu: a vGPU
536fc234074b09 Changbin Du 2017-01-13 316 * @primary: is the vGPU presented as primary
536fc234074b09 Changbin Du 2017-01-13 317 *
536fc234074b09 Changbin Du 2017-01-13 318 */
536fc234074b09 Changbin Du 2017-01-13 319 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
536fc234074b09 Changbin Du 2017-01-13 320 bool primary)
536fc234074b09 Changbin Du 2017-01-13 321 {
536fc234074b09 Changbin Du 2017-01-13 322 struct intel_gvt *gvt = vgpu->gvt;
9ff06c38530099 Thomas Zimmermann 2021-01-28 323 struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev);
536fc234074b09 Changbin Du 2017-01-13 324 const struct intel_gvt_device_info *info = &gvt->device_info;
536fc234074b09 Changbin Du 2017-01-13 325 u16 *gmch_ctl;
ba25d977571e15 Colin Xu 2020-07-09 326 u8 next;
536fc234074b09 Changbin Du 2017-01-13 327
536fc234074b09 Changbin Du 2017-01-13 328 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
536fc234074b09 Changbin Du 2017-01-13 329 info->cfg_space_size);
536fc234074b09 Changbin Du 2017-01-13 330
536fc234074b09 Changbin Du 2017-01-13 331 if (!primary) {
536fc234074b09 Changbin Du 2017-01-13 332 vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =
536fc234074b09 Changbin Du 2017-01-13 333 INTEL_GVT_PCI_CLASS_VGA_OTHER;
536fc234074b09 Changbin Du 2017-01-13 334 vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =
536fc234074b09 Changbin Du 2017-01-13 335 INTEL_GVT_PCI_CLASS_VGA_OTHER;
536fc234074b09 Changbin Du 2017-01-13 336 }
536fc234074b09 Changbin Du 2017-01-13 337
536fc234074b09 Changbin Du 2017-01-13 338 /* Show guest that there isn't any stolen memory.*/
536fc234074b09 Changbin Du 2017-01-13 339 gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);
536fc234074b09 Changbin Du 2017-01-13 340 *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT);
536fc234074b09 Changbin Du 2017-01-13 341
536fc234074b09 Changbin Du 2017-01-13 342 intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,
536fc234074b09 Changbin Du 2017-01-13 343 gvt_aperture_pa_base(gvt), true);
536fc234074b09 Changbin Du 2017-01-13 344
536fc234074b09 Changbin Du 2017-01-13 345 vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
536fc234074b09 Changbin Du 2017-01-13 346 | PCI_COMMAND_MEMORY
536fc234074b09 Changbin Du 2017-01-13 347 | PCI_COMMAND_MASTER);
536fc234074b09 Changbin Du 2017-01-13 348 /*
536fc234074b09 Changbin Du 2017-01-13 349 * Clear the bar upper 32bit and let guest to assign the new value
536fc234074b09 Changbin Du 2017-01-13 350 */
536fc234074b09 Changbin Du 2017-01-13 351 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
536fc234074b09 Changbin Du 2017-01-13 352 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
f1751362d6357a Changbin Du 2017-08-18 353 memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
536fc234074b09 Changbin Du 2017-01-13 354 memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
536fc234074b09 Changbin Du 2017-01-13 355
f1751362d6357a Changbin Du 2017-08-18 356 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
6bba2b30d29cbb Piotr Piórkowski 2022-08-05 @357 pci_resource_len(pdev, GTTMMADR_BAR);
f1751362d6357a Changbin Du 2017-08-18 358 vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
1c3b5abb99542a Ville Syrjälä 2022-10-05 @359 pci_resource_len(pdev, GMADR_BAR);
c4270d122ccff9 Changbin Du 2017-11-02 360
c4270d122ccff9 Changbin Du 2017-11-02 361 memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
ba25d977571e15 Colin Xu 2020-07-09 362
ba25d977571e15 Colin Xu 2020-07-09 363 /* PM Support */
ba25d977571e15 Colin Xu 2020-07-09 364 vgpu->cfg_space.pmcsr_off = 0;
ba25d977571e15 Colin Xu 2020-07-09 365 if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {
ba25d977571e15 Colin Xu 2020-07-09 366 next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];
ba25d977571e15 Colin Xu 2020-07-09 367 do {
ba25d977571e15 Colin Xu 2020-07-09 368 if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {
ba25d977571e15 Colin Xu 2020-07-09 369 vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL;
ba25d977571e15 Colin Xu 2020-07-09 370 break;
ba25d977571e15 Colin Xu 2020-07-09 371 }
ba25d977571e15 Colin Xu 2020-07-09 372 next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];
ba25d977571e15 Colin Xu 2020-07-09 373 } while (next);
ba25d977571e15 Colin Xu 2020-07-09 374 }
536fc234074b09 Changbin Du 2017-01-13 375 }
c64ff6c774413f Changbin Du 2017-01-13 376
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index dca6003ccac8..389ccdc46a1e 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -101,9 +101,9 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) rsc[0].flags = IORESOURCE_IRQ; rsc[0].name = "hdmi-lpe-audio-irq"; - rsc[1].start = pci_resource_start(pdev, GTTMMADR_BAR) + + rsc[1].start = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + I915_HDMI_LPE_AUDIO_BASE; - rsc[1].end = pci_resource_start(pdev, GTTMMADR_BAR) + + rsc[1].end = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + I915_HDMI_LPE_AUDIO_BASE + I915_HDMI_LPE_AUDIO_SIZE - 1; rsc[1].flags = IORESOURCE_MEM; rsc[1].name = "hdmi-lpe-audio-mmio"; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index b31fe0fb013f..668131c25da7 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -871,8 +871,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) u32 pte_flags; int ret; - GEM_WARN_ON(pci_resource_len(pdev, GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); - phys_addr = pci_resource_start(pdev, GTTMMADR_BAR) + gen6_gttadr_offset(i915); + GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915)); + phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915); /* * On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range @@ -932,10 +932,10 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) u16 snb_gmch_ctl; if (!HAS_LMEM(i915) && !HAS_BAR2_SMEM_STOLEN(i915)) { - if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) + if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR)) return -ENXIO; - ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); + ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR); ggtt->mappable_end = resource_size(&ggtt->gmadr); } @@ -1089,10 +1089,10 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) unsigned int size; u16 snb_gmch_ctl; - if (!i915_pci_resource_valid(pdev, GTT_APERTURE_BAR)) + if (!i915_pci_resource_valid(pdev, GEN4_GMADR_BAR)) return -ENXIO; - ggtt->gmadr = pci_resource(pdev, GTT_APERTURE_BAR); + ggtt->gmadr = pci_resource(pdev, GEN4_GMADR_BAR); ggtt->mappable_end = resource_size(&ggtt->gmadr); /* diff --git a/drivers/gpu/drm/i915/gvt/cfg_space.c b/drivers/gpu/drm/i915/gvt/cfg_space.c index eef3bba8a41b..19a663f6504f 100644 --- a/drivers/gpu/drm/i915/gvt/cfg_space.c +++ b/drivers/gpu/drm/i915/gvt/cfg_space.c @@ -356,7 +356,7 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size = pci_resource_len(pdev, GTTMMADR_BAR); vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size = - pci_resource_len(pdev, GTT_APERTURE_BAR); + pci_resource_len(pdev, GMADR_BAR); memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4); diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h index 305f137d2ebd..ffe9e6a94a04 100644 --- a/drivers/gpu/drm/i915/intel_pci_config.h +++ b/drivers/gpu/drm/i915/intel_pci_config.h @@ -7,17 +7,26 @@ #define __INTEL_PCI_CONFIG_H__ /* PCI BARs */ -#define GTTMMADR_BAR 0 -#define GEN2_GTTMMADR_BAR 1 -#define GFXMEM_BAR 2 -#define GTT_APERTURE_BAR GFXMEM_BAR -#define GEN12_LMEM_BAR GFXMEM_BAR +#define GEN2_GMADR_BAR 0 +#define GEN2_MMADR_BAR 1 /* MMIO+GTT, despite the name */ + +#define GEN3_MMADR_BAR 0 /* MMIO only */ +#define GEN3_IO_BAR 1 +#define GEN3_GMADR_BAR 2 +#define GEN3_GTTADR_BAR 3 /* GTT only */ + +#define GEN4_GTTMMADR_BAR 0 /* MMIO+GTT */ +#define GEN4_GMADR_BAR 2 +#define GEN4_IO_BAR 4 + +#define GEN12_LMEM_BAR 2 static inline int intel_mmio_bar(int graphics_ver) { switch (graphics_ver) { - case 2: return GEN2_GTTMMADR_BAR; - default: return GTTMMADR_BAR; + case 2: return GEN2_MMADR_BAR; + case 3: return GEN3_MMADR_BAR; + default: return GEN4_GTTMMADR_BAR; } }