| Message ID | 20221010181434.513477-16-umesh.nerlige.ramappa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DG2 OA support | expand |
On Mon, 10 Oct 2022 11:14:33 -0700, Umesh Nerlige Ramappa wrote: > > From: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > We have an additional register to select which slices contribute to > OAG/OAG counter increments. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/i915_perf.c | 13 +++++++++++++ > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 4 files changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index ccd54ff54002..992ca7b0aea0 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -904,6 +904,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define HAS_OA_BPC_REPORTING(dev_priv) \ > (INTEL_INFO(dev_priv)->has_oa_bpc_reporting) > +#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \ > + (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits) If this is just for XEHPSDV maybe we could just have a platform check rather than introduce a flag? Otherwise this is: Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
On Mon, Oct 10, 2022 at 05:34:10PM -0700, Dixit, Ashutosh wrote: >On Mon, 10 Oct 2022 11:14:33 -0700, Umesh Nerlige Ramappa wrote: >> >> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com> >> >> We have an additional register to select which slices contribute to >> OAG/OAG counter increments. >> >> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 2 ++ >> drivers/gpu/drm/i915/i915_pci.c | 1 + >> drivers/gpu/drm/i915/i915_perf.c | 13 +++++++++++++ >> drivers/gpu/drm/i915/intel_device_info.h | 1 + >> 4 files changed, 17 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index ccd54ff54002..992ca7b0aea0 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -904,6 +904,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, >> >> #define HAS_OA_BPC_REPORTING(dev_priv) \ >> (INTEL_INFO(dev_priv)->has_oa_bpc_reporting) >> +#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \ >> + (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits) > >If this is just for XEHPSDV maybe we could just have a platform check >rather than introduce a flag? Otherwise this is: I think when it was added, it was only xehpsdv, but now applies to dg2 and some other platforms. Thanks, Umesh > >Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ccd54ff54002..992ca7b0aea0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -904,6 +904,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_OA_BPC_REPORTING(dev_priv) \ (INTEL_INFO(dev_priv)->has_oa_bpc_reporting) +#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \ + (INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits) /* * Set this flag, when platform requires 64K GTT page sizes or larger for diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6b25e4cb6221..f5de5ae0b800 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1023,6 +1023,7 @@ static const struct intel_device_info adl_p_info = { .has_logical_ring_elsq = 1, \ .has_mslice_steering = 1, \ .has_oa_bpc_reporting = 1, \ + .has_oa_slice_contrib_limits = 1, \ .has_rc6 = 1, \ .has_reset_engine = 1, \ .has_rps = 1, \ diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index ae7efe8a831e..c9ab7eaa15ea 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -4258,6 +4258,11 @@ static const struct i915_range gen12_oa_b_counters[] = { {} }; +static const struct i915_range xehp_oa_b_counters[] = { + { .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */ + { .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */ +}; + static const struct i915_range gen7_oa_mux_regs[] = { { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */ { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */ @@ -4332,6 +4337,12 @@ static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr) return reg_in_range_table(addr, gen12_oa_b_counters); } +static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr) +{ + return reg_in_range_table(addr, xehp_oa_b_counters) || + reg_in_range_table(addr, gen12_oa_b_counters); +} + static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr) { return reg_in_range_table(addr, gen12_oa_mux_regs); @@ -4844,6 +4855,8 @@ void i915_perf_init(struct drm_i915_private *i915) perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read; } else if (GRAPHICS_VER(i915) == 12) { perf->ops.is_valid_b_counter_reg = + HAS_OA_SLICE_CONTRIB_LIMITS(i915) ? + xehp_is_valid_b_counter_addr : gen12_is_valid_b_counter_addr; perf->ops.is_valid_mux_reg = gen12_is_valid_mux_addr; diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 1f7a842cd408..9975f736bc41 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -165,6 +165,7 @@ enum intel_ppgtt_type { func(has_media_ratio_mode); \ func(has_mslice_steering); \ func(has_oa_bpc_reporting); \ + func(has_oa_slice_contrib_limits); \ func(has_one_eu_per_fuse_bit); \ func(has_pxp); \ func(has_rc6); \