From patchwork Thu Oct 13 23:32:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 13006556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65177C433FE for ; Thu, 13 Oct 2022 23:32:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E9C2810E9EB; Thu, 13 Oct 2022 23:32:41 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 87B6F10E9EC for ; Thu, 13 Oct 2022 23:32:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665703955; x=1697239955; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C+hJ0Spj7SljE3vzwzJUtW3D6iIYSz2aTeuPV0JV6Bs=; b=BziN2dM8sQ/F1c33/d9h/PbwYbuSk84miVo2IFzJWZAZJUd3Nfb3OUeF 6pY/rgPKswq1Mip5FQUJPVGqUD+3e5YYwSBaqQwrfl0mgk0eWjKkDfFrI e4aahgO7zZyqPPnWji2pHZLFoHb6e+QUfw+GADbd6kldVjO12ZnGK0env L28xQ8raOdhZuubAZrJk7zyQM0ylAI3dI1+wZ8oYxwhCIhjmFpuEvGJtL B2/ZWI9iVOEnXaeqxggzAAdgNSDYQf92uSGdLRvn+aBCtmg61mVY77vbU 8k1lStdR813AunNMFSA7e82eCpmmDQGw1wjnI+c/BUwT5MHw9z5wEQ/lC g==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="292585208" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="292585208" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 16:32:35 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="752714462" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="752714462" Received: from anushasr-mobl7.jf.intel.com ([10.24.14.105]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 16:32:35 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 13 Oct 2022 16:32:23 -0700 Message-Id: <20221013233223.103381-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013233223.103381-1-anusha.srivatsa@intel.com> References: <20221013233223.103381-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/display: Add CDCLK Support for MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per bSpec MTL has 38.4 MHz Reference clock. MTL does support squasher like DG2 but only for lower frequencies. Change the has_cdclk_squasher() helper to reflect this. v2: Revert to using bxt_get_cdclk() BSpec: 65243 Cc: Radhakrishna Sripada Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 24 ++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 430b4cb0a8ab..f44cffeb1f94 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1222,7 +1222,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) static bool has_cdclk_squasher(struct drm_i915_private *i915) { - return IS_DG2(i915); + return DISPLAY_VER(i915) >= 14 || IS_DG2(i915); } struct intel_cdclk_vals { @@ -1350,6 +1350,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals mtl_cdclk_table[] = { + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a }, + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 }, + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 }, + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 }, + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 }, + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 }, + {} +}; + static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) { const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; @@ -3149,6 +3159,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) return freq; } +static const struct intel_cdclk_funcs mtl_cdclk_funcs = { + .get_cdclk = bxt_get_cdclk, + .set_cdclk = bxt_set_cdclk, + .modeset_calc_cdclk = bxt_modeset_calc_cdclk, + .calc_voltage_level = tgl_calc_voltage_level, +}; + static const struct intel_cdclk_funcs tgl_cdclk_funcs = { .get_cdclk = bxt_get_cdclk, .set_cdclk = bxt_set_cdclk, @@ -3284,7 +3301,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { */ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) { - if (IS_DG2(dev_priv)) { + if (IS_METEORLAKE(dev_priv)) { + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; + dev_priv->display.cdclk.table = mtl_cdclk_table; + } else if (IS_DG2(dev_priv)) { dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; dev_priv->display.cdclk.table = dg2_cdclk_table; } else if (IS_ALDERLAKE_P(dev_priv)) {