diff mbox series

[12/20] drm/i915/mtl: Add voltage swing sequence for C20

Message ID 20221014124740.774835-13-mika.kahola@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/mtl: Add C10 and C20 phy support | expand

Commit Message

Mika Kahola Oct. 14, 2022, 12:47 p.m. UTC 
DP1.4 and DP20 voltage swing sequence for C20 phy.

Bspec: 65449, 67636, 67610

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 31 ++++++++++++-----
 .../gpu/drm/i915/display/intel_cx0_reg_defs.h |  4 +++
 .../drm/i915/display/intel_ddi_buf_trans.c    | 33 +++++++++++++++++--
 3 files changed, 58 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 088f59c26dde..aab606520a62 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -340,14 +340,29 @@  void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 		lane = ln / 2;
 		tx = ln % 2 + 1;
 
-		intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
-			      C10_PHY_VSWING_PREEMPH_MASK,
-			      C10_PHY_VSWING_PREEMPH(trans->entries[level].direct.preemph),
-			      MB_WRITE_COMMITTED);
-		intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 8),
-			      C10_PHY_VSWING_LEVEL_MASK,
-			      C10_PHY_VSWING_LEVEL(trans->entries[level].direct.level),
-			      MB_WRITE_COMMITTED);
+		if (crtc_state->port_clock > 1000000) {
+			intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
+				      C20_PHY_VSWING_PREEMPH_MASK,
+				      C20_PHY_VSWING_PREEMPH(trans->entries[level].snps.pre_cursor),
+				      MB_WRITE_COMMITTED);
+			intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 3),
+				      C20_PHY_VSWING_PREEMPH_MASK,
+				      C20_PHY_VSWING_PREEMPH(trans->entries[level].snps.vswing),
+				      MB_WRITE_COMMITTED);
+			intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 4),
+				      C20_PHY_VSWING_PREEMPH_MASK,
+				      C20_PHY_VSWING_PREEMPH(trans->entries[level].snps.post_cursor),
+				      MB_WRITE_COMMITTED);
+		} else {
+			intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
+				      C10_PHY_VSWING_PREEMPH_MASK,
+				      C10_PHY_VSWING_PREEMPH(trans->entries[level].direct.preemph),
+				      MB_WRITE_COMMITTED);
+			intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 8),
+				      C10_PHY_VSWING_LEVEL_MASK,
+				      C10_PHY_VSWING_LEVEL(trans->entries[level].direct.level),
+				      MB_WRITE_COMMITTED);
+		}
 	}
 
 	intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index b3912d15a823..de5bce5037dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -198,6 +198,10 @@ 
 #define C20_MPLLB_TX_CLK_DIV_MASK	REG_GENMASK(15, 13)
 #define C20_MPLLA_TX_CLK_DIV_MASK	REG_GENMASK(10, 8)
 
+/* C20 Phy VSwing Masks */
+#define C20_PHY_VSWING_PREEMPH_MASK	REG_GENMASK8(5, 0)
+#define C20_PHY_VSWING_PREEMPH(val)	REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
+
 #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx)	(0x303D + (idx))
 
 #endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 49f8a0a6593b..916b5dc28abe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -9,6 +9,7 @@ 
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_cx0_phy.h"
 
 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  * them for both DP and FDI transports, allowing those ports to
@@ -1053,12 +1054,37 @@  static const union intel_ddi_buf_trans_entry direct_map_trans[] = {
     { .direct = { .level = 3, .preemph = 0 } },
 };
 
-static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
+static const struct intel_ddi_buf_trans mtl_cx0_trans = {
 	.entries = direct_map_trans,
 	.num_entries = ARRAY_SIZE(direct_map_trans),
 	.hdmi_default_entry = ARRAY_SIZE(direct_map_trans) - 1,
 };
 
+/* DP2.0 */
+static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
+	{ .snps = { 48, 0, 0 } },       /* preset 0 */
+	{ .snps = { 43, 0, 5 } },       /* preset 1 */
+	{ .snps = { 40, 0, 8 } },       /* preset 2 */
+	{ .snps = { 37, 0, 11 } },      /* preset 3 */
+	{ .snps = { 33, 0, 15 } },      /* preset 4 */
+	{ .snps = { 46, 2, 0 } },       /* preset 5 */
+	{ .snps = { 42, 2, 4 } },       /* preset 6 */
+	{ .snps = { 38, 2, 8 } },       /* preset 7 */
+	{ .snps = { 35, 2, 11 } },      /* preset 8 */
+	{ .snps = { 33, 2, 13 } },      /* preset 9 */
+	{ .snps = { 44, 4, 0 } },       /* preset 10 */
+	{ .snps = { 40, 4, 4 } },       /* preset 11 */
+	{ .snps = { 37, 4, 7 } },       /* preset 12 */
+	{ .snps = { 33, 4, 11 } },      /* preset 13 */
+	{ .snps = { 36, 6, 6 } },       /* preset 14 */
+	{ .snps = { 28, 6, 2 } },       /* preset 15 */
+};
+
+static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
+	.entries = _mtl_c20_trans_uhbr,
+	.num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
+};
+
 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
 {
 	return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1635,7 +1661,10 @@  mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
 		      const struct intel_crtc_state *crtc_state,
 		      int *n_entries)
 {
-	return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
+	if (crtc_state->port_clock > 1000000)
+		return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
+	else
+		return intel_get_buf_trans(&mtl_cx0_trans, n_entries);
 }
 
 void intel_ddi_buf_trans_init(struct intel_encoder *encoder)