| Message ID | 20221014124740.774835-21-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Add C10 and C20 phy support | expand |
On Fri, Oct 14, 2022 at 03:47:40PM +0300, Mika Kahola wrote: > From: Anusha Srivatsa <anusha.srivatsa@intel.com> > > Unlike previous platforms that used PORT_TX_DFLEXDPSP > for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1 > from which the max_lanes has to be calculated. > > Bspec: 50235, 65380 > Cc: Mika Kahola <mika.kahola@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_tc.c | 30 +++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c > index dba10bcc6b66..1bc81adf1ad7 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -13,6 +13,10 @@ > #include "intel_tc.h" > #include "intel_tc_phy_regs.h" > > +#define DP_PIN_ASSIGNMENT_C 0x3 > +#define DP_PIN_ASSIGNMENT_D 0x4 > +#define DP_PIN_ASSIGNMENT_E 0x5 The above are flags for the PORT_TX_DFLEXPA1 register, so should be defined next to it. TGL handles a few more encodings, not sure if that's correct or the register description, opened a bspec ticket to clarify that. > + > static const char *tc_port_mode_name(enum tc_port_mode mode) > { > static const char * const names[] = { > @@ -149,6 +153,29 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) > DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); > } > > +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) The function returns the maximum number of lanes, so should be named accordingly. > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + intel_wakeref_t wakeref; > + u32 pin_mask; > + > + assert_tc_cold_blocked(dig_port); > + > + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) > + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); The called function handles all the above, so it can be just: switch (intel_tc_port_get_pin_assignment_mask()): > + > + switch(pin_mask) { > + default: > + MISSING_CASE(pin_mask); > + fallthrough; > + case DP_PIN_ASSIGNMENT_D: > + return 2; > + case DP_PIN_ASSIGNMENT_C: > + case DP_PIN_ASSIGNMENT_E: > + return 4; > + } > +} > + > int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) > { > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > @@ -158,6 +185,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) > if (dig_port->tc_mode != TC_PORT_DP_ALT) > return 4; > > + if (DISPLAY_VER(i915) >= 14) > + return mtl_tc_port_get_pin_assignment_mask(dig_port); > + > assert_tc_cold_blocked(dig_port); > > lane_mask = 0; > -- > 2.34.1 >
> -----Original Message----- > From: Deak, Imre <imre.deak@intel.com> > Sent: Wednesday, October 26, 2022 5:27 PM > To: Kahola, Mika <mika.kahola@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha > <anusha.srivatsa@intel.com>; Roper, Matthew D > <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com> > Subject: Re: [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC > > On Fri, Oct 14, 2022 at 03:47:40PM +0300, Mika Kahola wrote: > > From: Anusha Srivatsa <anusha.srivatsa@intel.com> > > > > Unlike previous platforms that used PORT_TX_DFLEXDPSP for max_lane > > calculation, MTL uses only PORT_TX_DFLEXPA1 from which the max_lanes > > has to be calculated. > > > > Bspec: 50235, 65380 > > Cc: Mika Kahola <mika.kahola@intel.com> > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > > Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_tc.c | 30 > > +++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c > > b/drivers/gpu/drm/i915/display/intel_tc.c > > index dba10bcc6b66..1bc81adf1ad7 100644 > > --- a/drivers/gpu/drm/i915/display/intel_tc.c > > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > > @@ -13,6 +13,10 @@ > > #include "intel_tc.h" > > #include "intel_tc_phy_regs.h" > > > > +#define DP_PIN_ASSIGNMENT_C 0x3 > > +#define DP_PIN_ASSIGNMENT_D 0x4 > > +#define DP_PIN_ASSIGNMENT_E 0x5 > > The above are flags for the PORT_TX_DFLEXPA1 register, so should be defined > next to it. Ok. I will move these defines to the correct place. > > TGL handles a few more encodings, not sure if that's correct or the register > description, opened a bspec ticket to clarify that. > > > + > > static const char *tc_port_mode_name(enum tc_port_mode mode) { > > static const char * const names[] = { @@ -149,6 +153,29 @@ u32 > > intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) > > DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); > > } > > > > +static int mtl_tc_port_get_pin_assignment_mask(struct > > +intel_digital_port *dig_port) > > The function returns the maximum number of lanes, so should be named > accordingly. Yes, I will figure out a different name for that function. > > > +{ > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + intel_wakeref_t wakeref; > > + u32 pin_mask; > > + > > + assert_tc_cold_blocked(dig_port); > > + > > + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, > wakeref) > > + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); > > The called function handles all the above, so it can be just: > > switch (intel_tc_port_get_pin_assignment_mask()): Yes. This simplifies the code a bit. Thanks for a review and comments! Cheers, Mika > > > + > > + switch(pin_mask) { > > + default: > > + MISSING_CASE(pin_mask); > > + fallthrough; > > + case DP_PIN_ASSIGNMENT_D: > > + return 2; > > + case DP_PIN_ASSIGNMENT_C: > > + case DP_PIN_ASSIGNMENT_E: > > + return 4; > > + } > > +} > > + > > int intel_tc_port_fia_max_lane_count(struct intel_digital_port > > *dig_port) { > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ > > -158,6 +185,9 @@ int intel_tc_port_fia_max_lane_count(struct > intel_digital_port *dig_port) > > if (dig_port->tc_mode != TC_PORT_DP_ALT) > > return 4; > > > > + if (DISPLAY_VER(i915) >= 14) > > + return mtl_tc_port_get_pin_assignment_mask(dig_port); > > + > > assert_tc_cold_blocked(dig_port); > > > > lane_mask = 0; > > -- > > 2.34.1 > >
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index dba10bcc6b66..1bc81adf1ad7 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -13,6 +13,10 @@ #include "intel_tc.h" #include "intel_tc_phy_regs.h" +#define DP_PIN_ASSIGNMENT_C 0x3 +#define DP_PIN_ASSIGNMENT_D 0x4 +#define DP_PIN_ASSIGNMENT_E 0x5 + static const char *tc_port_mode_name(enum tc_port_mode mode) { static const char * const names[] = { @@ -149,6 +153,29 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); } +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + intel_wakeref_t wakeref; + u32 pin_mask; + + assert_tc_cold_blocked(dig_port); + + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); + + switch(pin_mask) { + default: + MISSING_CASE(pin_mask); + fallthrough; + case DP_PIN_ASSIGNMENT_D: + return 2; + case DP_PIN_ASSIGNMENT_C: + case DP_PIN_ASSIGNMENT_E: + return 4; + } +} + int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -158,6 +185,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) if (dig_port->tc_mode != TC_PORT_DP_ALT) return 4; + if (DISPLAY_VER(i915) >= 14) + return mtl_tc_port_get_pin_assignment_mask(dig_port); + assert_tc_cold_blocked(dig_port); lane_mask = 0;