diff mbox series

[v2] drm/1915/guc: enable engine reset on CAT

Message ID 20221019145452.256254-1-andrzej.hajda@intel.com (mailing list archive)
State New, archived
Headers show
Series [v2] drm/1915/guc: enable engine reset on CAT | expand

Commit Message

Andrzej Hajda Oct. 19, 2022, 2:54 p.m. UTC
In case of catastrophic errors GuC is able to initate engine
reset immediately, instead of waiting for timeout.

Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
v2: added GuC version check (John)
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.c      | 3 +++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
 2 files changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 27b09ba1d295fc..9b6f6b9be02874 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -213,6 +213,9 @@  static u32 guc_ctl_feature_flags(struct intel_guc *guc)
 {
 	u32 flags = 0;
 
+	if (GET_UC_VER(guc) >= MAKE_UC_VER(67, 0, 0))
+		flags = GUC_CTL_ENABLE_ENGINE_RESET_ON_CAT;
+
 	if (!intel_guc_submission_is_used(guc))
 		flags |= GUC_CTL_DISABLE_SCHEDULER;
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index e7a7fb450f442a..96f3116e263cdf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -109,6 +109,7 @@ 
 
 #define GUC_CTL_FEATURE			2
 #define   GUC_CTL_ENABLE_SLPC		BIT(2)
+#define   GUC_CTL_ENABLE_ENGINE_RESET_ON_CAT BIT(8)
 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
 
 #define GUC_CTL_DEBUG			3