diff mbox series

[3/5] drm/i915/mtl: Modify CAGF functions for MTL

Message ID 20221019233721.3270601-4-ashutosh.dixit@intel.com (mailing list archive)
State New, archived
Headers show
Series i915: CAGF and RC6 changes for MTL | expand

Commit Message

Dixit, Ashutosh Oct. 19, 2022, 11:37 p.m. UTC 
From: Badal Nilawar <badal.nilawar@intel.com>

Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.

v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
    Move MTL branches in cagf functions to top (MattR)
    Fix commit message (Andi)
v3: Added comment about registers not needing forcewake for Gen12+ and
    returning 0 freq in RC6
v4: Use REG_FIELD_GET and uncore (Rodrigo)

Bspec: 66300

Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h |  4 ++++
 drivers/gpu/drm/i915/gt/intel_rps.c     | 12 ++++++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

Comments

Dixit, Ashutosh Oct. 21, 2022, 4:02 p.m. UTC | #1 
On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
>
> From: Badal Nilawar <badal.nilawar@intel.com>
>
> Update CAGF functions for MTL to get actual resolved frequency of 3D and
> SAMedia.
>
> v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
>     Move MTL branches in cagf functions to top (MattR)
>     Fix commit message (Andi)
> v3: Added comment about registers not needing forcewake for Gen12+ and
>     returning 0 freq in RC6
> v4: Use REG_FIELD_GET and uncore (Rodrigo)
>
> Bspec: 66300

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h |  4 ++++
>  drivers/gpu/drm/i915/gt/intel_rps.c     | 12 ++++++++++--
>  2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index f8c4f758ac0b1..d8dbd0ac3b064 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -21,6 +21,10 @@
>   */
>  #define PERF_REG(offset)			_MMIO(offset)
>
> +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> +#define MTL_MIRROR_TARGET_WP1			_MMIO(0xc60)
> +#define   MTL_CAGF_MASK				REG_GENMASK(8, 0)
> +
>  /* RPM unit config (Gen8+) */
>  #define RPM_CONFIG0				_MMIO(0xd00)
>  #define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index da6b969f554b6..63cc7c538401e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>	struct drm_i915_private *i915 = rps_to_i915(rps);
>	u32 cagf;
>
> -	if (GRAPHICS_VER(i915) >= 12)
> +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> +		cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
> +	else if (GRAPHICS_VER(i915) >= 12)
>		cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
>	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>		cagf = REG_FIELD_GET(RPE_MASK, rpstat);
> @@ -2115,7 +2117,13 @@ static u32 read_cagf(struct intel_rps *rps)
>	struct intel_uncore *uncore = rps_to_uncore(rps);
>	u32 freq;
>
> -	if (GRAPHICS_VER(i915) >= 12) {
> +	/*
> +	 * For Gen12+ reading freq from HW does not need a forcewake and
> +	 * registers will return 0 freq when GT is in RC6
> +	 */
> +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> +		freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> +	} else if (GRAPHICS_VER(i915) >= 12) {
>		freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
>	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
>		vlv_punit_get(i915);
> --
> 2.38.0
>
Rodrigo Vivi Oct. 21, 2022, 4:12 p.m. UTC | #2 
On Fri, Oct 21, 2022 at 09:02:03AM -0700, Dixit, Ashutosh wrote:
> On Wed, 19 Oct 2022 16:37:19 -0700, Ashutosh Dixit wrote:
> >
> > From: Badal Nilawar <badal.nilawar@intel.com>
> >
> > Update CAGF functions for MTL to get actual resolved frequency of 3D and
> > SAMedia.
> >
> > v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
> >     Move MTL branches in cagf functions to top (MattR)
> >     Fix commit message (Andi)
> > v3: Added comment about registers not needing forcewake for Gen12+ and
> >     returning 0 freq in RC6
> > v4: Use REG_FIELD_GET and uncore (Rodrigo)
> >
> > Bspec: 66300
> 
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> >
> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gt_regs.h |  4 ++++
> >  drivers/gpu/drm/i915/gt/intel_rps.c     | 12 ++++++++++--
> >  2 files changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index f8c4f758ac0b1..d8dbd0ac3b064 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -21,6 +21,10 @@
> >   */
> >  #define PERF_REG(offset)			_MMIO(offset)
> >
> > +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
> > +#define MTL_MIRROR_TARGET_WP1			_MMIO(0xc60)
> > +#define   MTL_CAGF_MASK				REG_GENMASK(8, 0)
> > +
> >  /* RPM unit config (Gen8+) */
> >  #define RPM_CONFIG0				_MMIO(0xd00)
> >  #define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index da6b969f554b6..63cc7c538401e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> >	struct drm_i915_private *i915 = rps_to_i915(rps);
> >	u32 cagf;
> >
> > -	if (GRAPHICS_VER(i915) >= 12)
> > +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > +		cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
> > +	else if (GRAPHICS_VER(i915) >= 12)
> >		cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
> >	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> >		cagf = REG_FIELD_GET(RPE_MASK, rpstat);
> > @@ -2115,7 +2117,13 @@ static u32 read_cagf(struct intel_rps *rps)
> >	struct intel_uncore *uncore = rps_to_uncore(rps);
> >	u32 freq;
> >
> > -	if (GRAPHICS_VER(i915) >= 12) {
> > +	/*
> > +	 * For Gen12+ reading freq from HW does not need a forcewake and
> > +	 * registers will return 0 freq when GT is in RC6
> > +	 */
> > +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > +		freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
> > +	} else if (GRAPHICS_VER(i915) >= 12) {
> >		freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
> >	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> >		vlv_punit_get(i915);
> > --
> > 2.38.0
> >
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f8c4f758ac0b1..d8dbd0ac3b064 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -21,6 +21,10 @@ 
  */
 #define PERF_REG(offset)			_MMIO(offset)
 
+/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
+#define MTL_MIRROR_TARGET_WP1			_MMIO(0xc60)
+#define   MTL_CAGF_MASK				REG_GENMASK(8, 0)
+
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0				_MMIO(0xd00)
 #define   GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index da6b969f554b6..63cc7c538401e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2093,7 +2093,9 @@  u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
 	struct drm_i915_private *i915 = rps_to_i915(rps);
 	u32 cagf;
 
-	if (GRAPHICS_VER(i915) >= 12)
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat);
+	else if (GRAPHICS_VER(i915) >= 12)
 		cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
 	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
 		cagf = REG_FIELD_GET(RPE_MASK, rpstat);
@@ -2115,7 +2117,13 @@  static u32 read_cagf(struct intel_rps *rps)
 	struct intel_uncore *uncore = rps_to_uncore(rps);
 	u32 freq;
 
-	if (GRAPHICS_VER(i915) >= 12) {
+	/*
+	 * For Gen12+ reading freq from HW does not need a forcewake and
+	 * registers will return 0 freq when GT is in RC6
+	 */
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
+		freq = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+	} else if (GRAPHICS_VER(i915) >= 12) {
 		freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
 	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
 		vlv_punit_get(i915);