| Message ID | 20221025180335.1723742-2-matthew.s.atwood@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915/dg2: Introduce Wa_18018764978 | expand |
On Tue, Oct 25, 2022 at 11:03:35AM -0700, Matt Atwood wrote: > Wa_18019271663 applies to all DG2 steppings and skus. > > Bspec:45809 Could we also add the reference to the BSpec containing the WA description? > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ++++--- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index e8372d4cd548..46035503068c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -421,9 +421,10 @@ > #define RC_OP_FLUSH_ENABLE (1 << 0) > #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) > #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ > -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) > -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) > -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) > +#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) > +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) > +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) > +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) > > #define GEN7_GT_MODE _MMIO(0x7008) > #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index ced3a26cf7e7..9f39b7758ff3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -750,6 +750,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > /* Wa_15010599737:dg2 */ > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > + > + /* Wa_18019271663:dg2 */ > + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > } > > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, > -- > 2.37.3 >
On Thu, Oct 27, 2022 at 02:28:53PM -0300, Gustavo Sousa wrote: > On Tue, Oct 25, 2022 at 11:03:35AM -0700, Matt Atwood wrote: > > Wa_18019271663 applies to all DG2 steppings and skus. > > > > Bspec:45809 > > Could we also add the reference to the BSpec containing the WA description? Good catch bspec ref should be 66622 > > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ++++--- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > > 2 files changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index e8372d4cd548..46035503068c 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -421,9 +421,10 @@ > > #define RC_OP_FLUSH_ENABLE (1 << 0) > > #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) > > #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ > > -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) > > -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) > > -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) > > +#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) > > +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) > > +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) > > +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) > > > > #define GEN7_GT_MODE _MMIO(0x7008) > > #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index ced3a26cf7e7..9f39b7758ff3 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -750,6 +750,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, > > > > /* Wa_15010599737:dg2 */ > > wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); > > + > > + /* Wa_18019271663:dg2 */ > > + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); > > } > > > > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, > > -- > > 2.37.3 > >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index e8372d4cd548..46035503068c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -421,9 +421,10 @@ #define RC_OP_FLUSH_ENABLE (1 << 0) #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) -#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) -#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) +#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) #define GEN7_GT_MODE _MMIO(0x7008) #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index ced3a26cf7e7..9f39b7758ff3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -750,6 +750,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_15010599737:dg2 */ wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); + + /* Wa_18019271663:dg2 */ + wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); } static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
Wa_18019271663 applies to all DG2 steppings and skus. Bspec:45809 Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 7 ++++--- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-)