| Message ID | 20221026162332.879648-1-andrzej.hajda@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/selftests: add over-fetch padding to store_dw batchbuffer | expand |
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c index 3c55e77b0f1b00..42966e3855a5a5 100644 --- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c +++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c @@ -44,13 +44,14 @@ igt_emit_store_dw(struct i915_vma *vma, unsigned long count, u32 val) { +#define BB_OVERFETCH_SIZE (PAGE_SIZE) struct drm_i915_gem_object *obj; const int ver = GRAPHICS_VER(vma->vm->i915); unsigned long n, size; u32 *cmd; int err; - size = (4 * count + 1) * sizeof(u32); + size = (4 * count + 1) * sizeof(u32) + BB_OVERFETCH_SIZE; size = round_up(size, PAGE_SIZE); obj = i915_gem_object_create_internal(vma->vm->i915, size); if (IS_ERR(obj))
Due to batch buffer over-fetch mechanism up to 4KB beyond the last command in the buffer can be read by engine executing the buffer. On the other side if memory is accessed during TLB invalidation proper TLB invalidation is not guaranteed. Both conditions can occur when two buffers are bound to adjacent PTEs and during execution of the 1st buffer (overfetch tries to access PTE of the 2nd buffer) 2nd buffer is removed (memory is unmapped and TLB is invalidated during memory access, not fully). As a result engine tries to access unmapped memory and causes DMAR faults and catastrophic errors. The simplest solution of this issue is to allocate buffers big enough, to avoid over-fetch crossing buffer boundary. BSpec: 45718, 44393 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5278 Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> --- drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)