@@ -2121,6 +2121,28 @@
#define TRANS_PUSH_EN REG_BIT(31)
#define TRANS_PUSH_SEND REG_BIT(30)
+/* HDMI 2.1 FRL Configuration */
+#define _TRANS_HDMI_FRL_CFG_A 0x600B0
+#define TRANS_HDMI_FRL_CFG(trans) _MMIO_TRANS2(trans, _TRANS_HDMI_FRL_CFG_A)
+#define TRANS_HDMI_FRL_ENABLE REG_BIT(31)
+#define TRANS_HDMI_TMDS_ENABLE 0
+#define TRANS_HDMI_FRL_TRAINING_COMPLETE REG_BIT(28)
+#define TRANS_HDMI_DISABLE_DFM_MASKING REG_BIT(20)
+#define TRANS_HDMI_R_B_SCHED_ENABLE_MASK REG_BIT(19)
+#define TRANS_HDMI_R_B_SCHED_ENABLE(val) REG_FIELD_PREP(TRANS_HDMI_R_B_SCHED_ENABLE_MASK, val)
+#define TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK REG_GENMASK(18, 16)
+#define TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(val) REG_FIELD_PREP(TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK, val)
+#define TRANS_HDMI_MIN_BLANK_CHAR_MASK REG_GENMASK(15, 12)
+#define TRANS_HDMI_MIN_BLANK_CHAR(val) REG_FIELD_PREP(TRANS_HDMI_MIN_BLANK_CHAR_MASK, val)
+#define TRANS_HDMI_MIN_BLANK_CHAR_VAL 0xA
+#define TRANS_HDMI_FRL_PKT_PAYLOAD_MAX_MASK REG_GENMASK(9, 0)
+#define TRANS_HDMI_FRL_PKT_PAYLOAD_MAX(val) REG_FIELD_PREP(TRANS_HDMI_FRL_PKT_PAYLOAD_MAX_MASK, val)
+#define TRANS_HDMI_PAYLOAD_UPPER_BOUND 0x3FE
+
+#define _TRANS_HDMI_FRL_TRAIN_A 0x600B4
+#define TRANS_HDMI_FRL_TRAIN(trans) _MMIO_TRANS2(trans, _TRANS_HDMI_FRL_TRAIN_A)
+#define TRANS_HDMI_FRL_LTP(pattern, lane) ((pattern) << (lane) * 8)
+
/*
* HSW+ eDP PSR registers
*
Add registers for FRL configuration. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)