diff mbox series

[RFC,08/15] drm/i915/mtl: Add HDMI2.1 bits in PORT_BUF_CTL_1

Message ID 20221107072045.628895-9-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series Add support for HDMI2.1 FRL | expand

Commit Message

Nautiyal, Ankit K Nov. 7, 2022, 7:20 a.m. UTC 
This patch adds bits related to HDMI2.1 in PORT_BUF_CTL_1 that
is needed to be programmed for D2D Interface for Ports in
IO expansion Die.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index dfe156141d73..efba0ce90229 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -66,14 +66,22 @@ 
 							 [PORT_TC4] = _XELPDP_PORT_BUF_CTL1_LN0_USBC4))
 
 #define XELPDP_PORT_BUF_CTL1(port)			_MMIO(_XELPDP_PORT_BUF_CTL1(port))
+#define  XELPDP_PORT_BUF_D2D_LINK_ENABLE		REG_BIT(29)
+#define  XELPDP_PORT_BUF_D2D_LINK_STATE			REG_BIT(28)
 #define  XELPDP_PORT_BUF_SOC_PHY_READY			REG_BIT(24)
 #define  XELPDP_PORT_REVERSAL				REG_BIT(16)
+#define  XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK		REG_GENMASK(19, 18)
+#define  XELPDP_PORT_BUF_PORT_DATA_10BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
+#define  XELPDP_PORT_BUF_PORT_DATA_20BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
+#define  XELPDP_PORT_BUF_PORT_DATA_40BIT		REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
 
+#define  XELPDP_PORT_BUF_PHY_IDLE			REG_BIT(7)
 #define  XELPDP_TC_PHY_OWNERSHIP			REG_BIT(6)
 #define  XELPDP_TCSS_POWER_REQUEST			REG_BIT(5)
 #define  XELPDP_TCSS_POWER_STATE			REG_BIT(4)
 #define  XELPDP_PORT_WIDTH_MASK				REG_GENMASK(3, 1)
 #define  XELPDP_PORT_WIDTH(val)				REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
+#define  XELPDP_PORT_HDMI_FRL_SHFTR_EN			REG_BIT(0)
 
 #define XELPDP_PORT_BUF_CTL2(port)			_MMIO(_XELPDP_PORT_BUF_CTL1(port) + 4)
 #define  XELPDP_LANE0_PIPE_RESET			REG_BIT(31)