diff mbox series

[v2,3/9] drm/i915: Use the AUX_IO power domain only for eDP/PSR port

Message ID 20221107170917.3566758-4-imre.deak@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/tgl+: Enable DC power states on all eDP ports | expand

Commit Message

Imre Deak Nov. 7, 2022, 5:09 p.m. UTC 
Use the AUX_IO_A display power domain only for eDP on port A where PSR
is also supported. This is the case where DC states need to be enabled
while the output is enabled - ensured by AUX_IO_A domain not enabling
the DC_OFF power well. Otherwise port A can be treated the same way as
other ports with an external DP output: using the AUX_<port> domain
which disables the unrequired DC states.

This change prepares for the next patch enabling DC states on all ports
supporting eDP/PSR besides port A.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e95bde5cf060e..4154f454ab52a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -846,7 +846,8 @@  bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 }
 
 static enum intel_display_power_domain
-intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
+intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
+			       const struct intel_crtc_state *crtc_state)
 {
 	/* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 	 * DC states enabled at the same time, while for driver initiated AUX
@@ -860,8 +861,10 @@  intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 	 * Note that PSR is enabled only on Port A even though this function
 	 * returns the correct domain for other ports too.
 	 */
-	return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
-					      intel_aux_power_domain(dig_port);
+	if (dig_port->aux_ch == AUX_CH_A && crtc_state->has_psr)
+		return POWER_DOMAIN_AUX_IO_A;
+	else
+		return intel_aux_power_domain(dig_port);
 }
 
 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
@@ -897,7 +900,8 @@  static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 		dig_port->aux_wakeref =
 			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port));
+						intel_ddi_main_link_aux_domain(dig_port,
+									       crtc_state));
 	}
 }
 
@@ -2739,7 +2743,8 @@  static void intel_ddi_post_disable(struct intel_atomic_state *state,
 
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
 		intel_display_power_put(dev_priv,
-					intel_ddi_main_link_aux_domain(dig_port),
+					intel_ddi_main_link_aux_domain(dig_port,
+								       old_crtc_state),
 					fetch_and_zero(&dig_port->aux_wakeref));
 
 	if (is_tc_port)
@@ -3065,7 +3070,8 @@  intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 		drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 		dig_port->aux_wakeref =
 			intel_display_power_get(dev_priv,
-						intel_ddi_main_link_aux_domain(dig_port));
+						intel_ddi_main_link_aux_domain(dig_port,
+									       crtc_state));
 	}
 
 	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))