| Message ID | 20221110150307.3366-4-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Panel replay phase1 implementation | expand |
Hi Animesh,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/Panel-replay-phase1-implementation/20221110-231024
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20221110150307.3366-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH 3/4] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-a013
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/f2cb0b05b6e1692eb2243960210676362e09c3af
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20221110-231024
git checkout f2cb0b05b6e1692eb2243960210676362e09c3af
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:3109:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +3109 drivers/gpu/drm/i915/display/intel_dp.c
3085
3086 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3087 struct dp_sdp *sdp, size_t size)
3088 {
3089 size_t length = sizeof(struct dp_sdp);
3090
3091 if (size < length)
3092 return -ENOSPC;
3093
3094 memset(sdp, 0, size);
3095
3096 /*
3097 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3098 * VSC SDP Header Bytes
3099 */
3100 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3101 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3102 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3103 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3104
3105 /*
3106 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
3107 * per DP 1.4a spec and DP 2.0 spec respectively.
3108 */
> 3109 if (vsc->revision != 0x5 || vsc->revision != 0x7)
3110 goto out;
3111
3112 /* VSC SDP Payload for DB16 through DB18 */
3113 /* Pixel Encoding and Colorimetry Formats */
3114 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3115 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3116
3117 switch (vsc->bpc) {
3118 case 6:
3119 /* 6bpc: 0x0 */
3120 break;
3121 case 8:
3122 sdp->db[17] = 0x1; /* DB17[3:0] */
3123 break;
3124 case 10:
3125 sdp->db[17] = 0x2;
3126 break;
3127 case 12:
3128 sdp->db[17] = 0x3;
3129 break;
3130 case 16:
3131 sdp->db[17] = 0x4;
3132 break;
3133 default:
3134 MISSING_CASE(vsc->bpc);
3135 break;
3136 }
3137 /* Dynamic Range and Component Bit Depth */
3138 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3139 sdp->db[17] |= 0x80; /* DB17[7] */
3140
3141 /* Content Type */
3142 sdp->db[18] = vsc->content_type & 0x7;
3143
3144 out:
3145 return length;
3146 }
3147
On Thu, 10 Nov 2022, Animesh Manna <animesh.manna@intel.com> wrote: > As panel replay feature similar to PSR feature of EDP panel, so currently > utilized existing psr framework for panel replay. > > Cc: Jouni Högander <jouni.hogander@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 15 +++++++ > drivers/gpu/drm/i915/display/intel_dp.c | 44 +++++++++++++++---- > drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++- > drivers/gpu/drm/i915/display/intel_psr.h | 1 + > 4 files changed, 93 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8da87cbb172b..3c126bf47119 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1623,6 +1623,8 @@ struct intel_psr { > bool irq_aux_error; > u16 su_w_granularity; > u16 su_y_granularity; > + bool source_panel_replay_support; > + bool sink_panel_replay_support; > u32 dc3co_exitline; > u32 dc3co_exit_delay; > struct delayed_work dc3co_work; > @@ -1926,6 +1928,11 @@ dp_to_lspcon(struct intel_dp *intel_dp) > #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ > (intel_dp)->psr.source_support) > > +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \ > + (intel_dp)->psr.source_panel_replay_support) > + > +#define IS_PANEL_REPLAY(intel_dp) (!intel_dp_is_edp(intel_dp)) > + > static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) > { > if (!intel_encoder_is_dp(encoder)) > @@ -1934,6 +1941,14 @@ static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) > return CAN_PSR(enc_to_intel_dp(encoder)); > } > > +static inline bool intel_encoder_can_panel_replay(struct intel_encoder *encoder) > +{ > + if (!intel_encoder_is_dp(encoder)) > + return false; > + > + return CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); > +} Instead of adding more of these in intel_display_types.h, please turn the relevant PSR macros and static inlines above into proper functions and move them to intel_psr.[ch]. Do that first. Name them accordingly. This file has to cease to be a dumping ground for random macros and static inlines. > + > static inline struct intel_digital_port * > hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) > { > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 7400d6b4c587..25bf18e40b96 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1726,12 +1726,23 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > - /* > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ > - * Colorimetry Format indication. > - */ > - vsc->revision = 0x5; > + if (crtc_state->has_psr && conn_state->connector->connector_type != > + DRM_MODE_CONNECTOR_eDP) { > + /* > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel > + * Encoding/Colorimetry Format indication. > + */ > + vsc->revision = 0x7; > + } else { > + /* > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ > + * Colorimetry Format indication. > + */ > + vsc->revision = 0x5; > + } > + > vsc->length = 0x13; > > /* DP 1.4a spec, Table 2-120 */ > @@ -1840,6 +1851,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, > vsc->revision = 0x4; > vsc->length = 0xe; > } > + } else if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) { > + if (intel_dp->psr.colorimetry_support && > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > + /* [Panel Replay with colorimetry info] */ > + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, > + vsc); > + } else { > + /* > + * [Panel Replay without colorimetry info] > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 > + * VSC SDP supporting 3D stereo + Panel Replay. > + */ > + vsc->revision = 0x6; > + vsc->length = 0x10; > + } > } else { > /* > * [PSR1] > @@ -3077,10 +3103,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ > > /* > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as > - * per DP 1.4a spec. > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as > + * per DP 1.4a spec and DP 2.0 spec respectively. > */ > - if (vsc->revision != 0x5) > + if (vsc->revision != 0x5 || vsc->revision != 0x7) > goto out; > > /* VSC SDP Payload for DB16 through DB18 */ > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index a75b37851504..50394143c798 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -983,6 +983,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, > &crtc_state->hw.adjusted_mode; > int psr_setup_time; > > + if (CAN_PANEL_REPLAY(intel_dp)) > + goto skip_psr_check; > /* > * Current PSR panels don't work reliably with VRR enabled > * So if VRR is enabled, do not enable PSR. > @@ -1026,8 +1028,14 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, > return; > } > > +skip_psr_check: > crtc_state->has_psr = true; > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); > + > + if (intel_dp_is_edp(intel_dp)) > + crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); > + > + if (IS_PANEL_REPLAY(intel_dp) && HAS_PSR2_SEL_FETCH(dev_priv)) > + crtc_state->has_psr2 = intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); > > crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); > intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, > @@ -2390,6 +2398,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, > } > } > > +/** > + * intel_panel_replay_init - Check for sink and source capability. > + * @intel_dp: Intel DP > + * > + * This function is called after the initializing connector. > + * (the initializing of connector treats the handling of connector capabilities) > + * And it initializes basic panel replay stuff for each DP Encoder. > + */ > +void intel_panel_replay_init(struct intel_dp *intel_dp) This can be static AFAICT, and there's no need for kernel-doc for static functions. > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + u8 pr_dpcd = 0; > + > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv))) Maybe HAS_PANEL_REPLAY() should include HAS_DP20() in its definition? > + return; > + > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); > + > + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { > + drm_dbg_kms(&dev_priv->drm, > + "Panel replay is not supported by panel\n"); > + return; > + } > + > + drm_dbg_kms(&dev_priv->drm, > + "Panel replay is supported by panel\n"); > + intel_dp->psr.sink_panel_replay_support = true; I don't see this reset anywhere. If you plug a panel replay display, unplug, plung a non-panel replay display, this remains true. > +} > + > /** > * intel_psr_init - Init basic PSR work and mutex. > * @intel_dp: Intel DP > @@ -2404,7 +2441,7 @@ void intel_psr_init(struct intel_dp *intel_dp) > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - if (!HAS_PSR(dev_priv)) > + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) > return; > > /* > @@ -2423,6 +2460,7 @@ void intel_psr_init(struct intel_dp *intel_dp) > } > > intel_dp->psr.source_support = true; > + intel_dp->psr.source_panel_replay_support = true; > > /* Set link_standby x link_off defaults */ > if (DISPLAY_VER(dev_priv) < 12) > @@ -2432,6 +2470,8 @@ void intel_psr_init(struct intel_dp *intel_dp) > INIT_WORK(&intel_dp->psr.work, intel_psr_work); > INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); > mutex_init(&intel_dp->psr.lock); > + > + intel_panel_replay_init(intel_dp); > } > > static int psr_get_status_and_error_status(struct intel_dp *intel_dp, > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h > index 2ac3a46cccc5..38e613990418 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.h > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > @@ -34,6 +34,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, > unsigned frontbuffer_bits, > enum fb_op_origin origin); > void intel_psr_init(struct intel_dp *intel_dp); > +void intel_panel_replay_init(struct intel_dp *intel_dp); > void intel_psr_compute_config(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state, > struct drm_connector_state *conn_state);
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of > Animesh Manna > Sent: Thursday, November 10, 2022 8:33 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 3/4] drm/i915/panelreplay: Initializaton and > compute config for panel replay > > As panel replay feature similar to PSR feature of EDP panel, so currently > utilized existing psr framework for panel replay. > > Cc: Jouni Högander <jouni.hogander@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 15 +++++++ > drivers/gpu/drm/i915/display/intel_dp.c | 44 +++++++++++++++---- > drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++- > drivers/gpu/drm/i915/display/intel_psr.h | 1 + > 4 files changed, 93 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8da87cbb172b..3c126bf47119 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1623,6 +1623,8 @@ struct intel_psr { > bool irq_aux_error; > u16 su_w_granularity; > u16 su_y_granularity; > + bool source_panel_replay_support; > + bool sink_panel_replay_support; > u32 dc3co_exitline; > u32 dc3co_exit_delay; > struct delayed_work dc3co_work; > @@ -1926,6 +1928,11 @@ dp_to_lspcon(struct intel_dp *intel_dp) #define > CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ > (intel_dp)->psr.source_support) > > +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)- > >psr.sink_panel_replay_support && \ > + (intel_dp)- > >psr.source_panel_replay_support) > + > +#define IS_PANEL_REPLAY(intel_dp) (!intel_dp_is_edp(intel_dp)) > + > static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { > if (!intel_encoder_is_dp(encoder)) > @@ -1934,6 +1941,14 @@ static inline bool intel_encoder_can_psr(struct > intel_encoder *encoder) > return CAN_PSR(enc_to_intel_dp(encoder)); > } > > +static inline bool intel_encoder_can_panel_replay(struct intel_encoder > +*encoder) { > + if (!intel_encoder_is_dp(encoder)) > + return false; > + > + return CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); > +} > + > static inline struct intel_digital_port * hdmi_to_dig_port(struct intel_hdmi > *intel_hdmi) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 7400d6b4c587..25bf18e40b96 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1726,12 +1726,23 @@ static void > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > - /* > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ > - * Colorimetry Format indication. > - */ > - vsc->revision = 0x5; > + if (crtc_state->has_psr && conn_state->connector->connector_type > != > + DRM_MODE_CONNECTOR_eDP) { > + /* > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel > + * Encoding/Colorimetry Format indication. > + */ > + vsc->revision = 0x7; > + } else { > + /* > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ > + * Colorimetry Format indication. > + */ > + vsc->revision = 0x5; > + } > + > vsc->length = 0x13; > > /* DP 1.4a spec, Table 2-120 */ > @@ -1840,6 +1851,21 @@ void intel_dp_compute_psr_vsc_sdp(struct > intel_dp *intel_dp, > vsc->revision = 0x4; > vsc->length = 0xe; > } > + } else if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) { > + if (intel_dp->psr.colorimetry_support && > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > + /* [Panel Replay with colorimetry info] */ > + intel_dp_compute_vsc_colorimetry(crtc_state, > conn_state, > + vsc); > + } else { > + /* > + * [Panel Replay without colorimetry info] > + * Prepare VSC Header for SU as per DP 2.0 spec, > Table 2-223 > + * VSC SDP supporting 3D stereo + Panel Replay. > + */ > + vsc->revision = 0x6; > + vsc->length = 0x10; > + } > } else { > /* > * [PSR1] > @@ -3077,10 +3103,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct > drm_dp_vsc_sdp *vsc, > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes > */ > > /* > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as > - * per DP 1.4a spec. > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format > as > + * per DP 1.4a spec and DP 2.0 spec respectively. > */ > - if (vsc->revision != 0x5) > + if (vsc->revision != 0x5 || vsc->revision != 0x7) > goto out; > > /* VSC SDP Payload for DB16 through DB18 */ diff --git > a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index a75b37851504..50394143c798 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -983,6 +983,8 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > &crtc_state->hw.adjusted_mode; > int psr_setup_time; > > + if (CAN_PANEL_REPLAY(intel_dp)) > + goto skip_psr_check; > /* > * Current PSR panels don't work reliably with VRR enabled > * So if VRR is enabled, do not enable PSR. > @@ -1026,8 +1028,14 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > return; > } > > +skip_psr_check: > crtc_state->has_psr = true; > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); > + > + if (intel_dp_is_edp(intel_dp)) > + crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, > crtc_state); > + > + if (IS_PANEL_REPLAY(intel_dp) && HAS_PSR2_SEL_FETCH(dev_priv)) > + crtc_state->has_psr2 = > intel_psr2_sel_fetch_config_valid(intel_dp, > +crtc_state); > > crtc_state->infoframes.enable |= > intel_hdmi_infoframe_enable(DP_SDP_VSC); > intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, > @@ -2390,6 +2398,35 @@ void intel_psr_flush(struct drm_i915_private > *dev_priv, > } > } > > +/** > + * intel_panel_replay_init - Check for sink and source capability. > + * @intel_dp: Intel DP > + * > + * This function is called after the initializing connector. > + * (the initializing of connector treats the handling of connector > +capabilities) > + * And it initializes basic panel replay stuff for each DP Encoder. > + */ > +void intel_panel_replay_init(struct intel_dp *intel_dp) { > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + u8 pr_dpcd = 0; > + > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv))) > + return; > + > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, > &pr_dpcd); > + > + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { > + drm_dbg_kms(&dev_priv->drm, > + "Panel replay is not supported by panel\n"); > + return; > + } > + > + drm_dbg_kms(&dev_priv->drm, > + "Panel replay is supported by panel\n"); > + intel_dp->psr.sink_panel_replay_support = true; } > + > /** > * intel_psr_init - Init basic PSR work and mutex. > * @intel_dp: Intel DP > @@ -2404,7 +2441,7 @@ void intel_psr_init(struct intel_dp *intel_dp) > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - if (!HAS_PSR(dev_priv)) > + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) > return; Should we continue initialization if PR is supported? > > /* > @@ -2423,6 +2460,7 @@ void intel_psr_init(struct intel_dp *intel_dp) > } > > intel_dp->psr.source_support = true; > + intel_dp->psr.source_panel_replay_support = true; > > /* Set link_standby x link_off defaults */ > if (DISPLAY_VER(dev_priv) < 12) > @@ -2432,6 +2470,8 @@ void intel_psr_init(struct intel_dp *intel_dp) > INIT_WORK(&intel_dp->psr.work, intel_psr_work); > INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, > tgl_dc3co_disable_work); > mutex_init(&intel_dp->psr.lock); > + > + intel_panel_replay_init(intel_dp); > } > > static int psr_get_status_and_error_status(struct intel_dp *intel_dp, diff --git > a/drivers/gpu/drm/i915/display/intel_psr.h > b/drivers/gpu/drm/i915/display/intel_psr.h > index 2ac3a46cccc5..38e613990418 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.h > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > @@ -34,6 +34,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, > unsigned frontbuffer_bits, > enum fb_op_origin origin); > void intel_psr_init(struct intel_dp *intel_dp); > +void intel_panel_replay_init(struct intel_dp *intel_dp); > void intel_psr_compute_config(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state, > struct drm_connector_state *conn_state); > -- > 2.29.0
> -----Original Message----- > From: Murthy, Arun R <arun.r.murthy@intel.com> > Sent: Friday, July 14, 2023 10:05 AM > To: Manna, Animesh <animesh.manna@intel.com>; intel- > gfx@lists.freedesktop.org > Subject: RE: [Intel-gfx] [PATCH 3/4] drm/i915/panelreplay: Initializaton and > compute config for panel replay > > > > > -----Original Message----- > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of > > Animesh Manna > > Sent: Thursday, November 10, 2022 8:33 PM > > To: intel-gfx@lists.freedesktop.org > > Subject: [Intel-gfx] [PATCH 3/4] drm/i915/panelreplay: Initializaton > > and compute config for panel replay > > > > As panel replay feature similar to PSR feature of EDP panel, so > > currently utilized existing psr framework for panel replay. > > > > Cc: Jouni Högander <jouni.hogander@intel.com> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > > --- > > .../drm/i915/display/intel_display_types.h | 15 +++++++ > > drivers/gpu/drm/i915/display/intel_dp.c | 44 +++++++++++++++---- > > drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++- > > drivers/gpu/drm/i915/display/intel_psr.h | 1 + > > 4 files changed, 93 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 8da87cbb172b..3c126bf47119 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1623,6 +1623,8 @@ struct intel_psr { > > bool irq_aux_error; > > u16 su_w_granularity; > > u16 su_y_granularity; > > + bool source_panel_replay_support; > > + bool sink_panel_replay_support; > > u32 dc3co_exitline; > > u32 dc3co_exit_delay; > > struct delayed_work dc3co_work; > > @@ -1926,6 +1928,11 @@ dp_to_lspcon(struct intel_dp *intel_dp) > > #define > > CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ > > (intel_dp)->psr.source_support) > > > > +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)- > > >psr.sink_panel_replay_support && \ > > + (intel_dp)- > > >psr.source_panel_replay_support) > > + > > +#define IS_PANEL_REPLAY(intel_dp) (!intel_dp_is_edp(intel_dp)) > > + > > static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { > > if (!intel_encoder_is_dp(encoder)) > > @@ -1934,6 +1941,14 @@ static inline bool intel_encoder_can_psr(struct > > intel_encoder *encoder) > > return CAN_PSR(enc_to_intel_dp(encoder)); > > } > > > > +static inline bool intel_encoder_can_panel_replay(struct > > +intel_encoder > > +*encoder) { > > + if (!intel_encoder_is_dp(encoder)) > > + return false; > > + > > + return CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); > > +} > > + > > static inline struct intel_digital_port * hdmi_to_dig_port(struct > > intel_hdmi > > *intel_hdmi) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 7400d6b4c587..25bf18e40b96 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -1726,12 +1726,23 @@ static void > > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > - /* > > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 > > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ > > - * Colorimetry Format indication. > > - */ > > - vsc->revision = 0x5; > > + if (crtc_state->has_psr && conn_state->connector->connector_type > > != > > + DRM_MODE_CONNECTOR_eDP) { > > + /* > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 > > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel > > + * Encoding/Colorimetry Format indication. > > + */ > > + vsc->revision = 0x7; > > + } else { > > + /* > > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 > > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ > > + * Colorimetry Format indication. > > + */ > > + vsc->revision = 0x5; > > + } > > + > > vsc->length = 0x13; > > > > /* DP 1.4a spec, Table 2-120 */ > > @@ -1840,6 +1851,21 @@ void intel_dp_compute_psr_vsc_sdp(struct > > intel_dp *intel_dp, > > vsc->revision = 0x4; > > vsc->length = 0xe; > > } > > + } else if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) { > > + if (intel_dp->psr.colorimetry_support && > > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { > > + /* [Panel Replay with colorimetry info] */ > > + intel_dp_compute_vsc_colorimetry(crtc_state, > > conn_state, > > + vsc); > > + } else { > > + /* > > + * [Panel Replay without colorimetry info] > > + * Prepare VSC Header for SU as per DP 2.0 spec, > > Table 2-223 > > + * VSC SDP supporting 3D stereo + Panel Replay. > > + */ > > + vsc->revision = 0x6; > > + vsc->length = 0x10; > > + } > > } else { > > /* > > * [PSR1] > > @@ -3077,10 +3103,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const > > struct drm_dp_vsc_sdp *vsc, > > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes > */ > > > > /* > > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as > > - * per DP 1.4a spec. > > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format > > as > > + * per DP 1.4a spec and DP 2.0 spec respectively. > > */ > > - if (vsc->revision != 0x5) > > + if (vsc->revision != 0x5 || vsc->revision != 0x7) > > goto out; > > > > /* VSC SDP Payload for DB16 through DB18 */ diff --git > > a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index a75b37851504..50394143c798 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -983,6 +983,8 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > &crtc_state->hw.adjusted_mode; > > int psr_setup_time; > > > > + if (CAN_PANEL_REPLAY(intel_dp)) > > + goto skip_psr_check; > > /* > > * Current PSR panels don't work reliably with VRR enabled > > * So if VRR is enabled, do not enable PSR. > > @@ -1026,8 +1028,14 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > return; > > } > > > > +skip_psr_check: > > crtc_state->has_psr = true; > > - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); > > + > > + if (intel_dp_is_edp(intel_dp)) > > + crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, > > crtc_state); > > + > > + if (IS_PANEL_REPLAY(intel_dp) && HAS_PSR2_SEL_FETCH(dev_priv)) > > + crtc_state->has_psr2 = > > intel_psr2_sel_fetch_config_valid(intel_dp, > > +crtc_state); > > > > crtc_state->infoframes.enable |= > > intel_hdmi_infoframe_enable(DP_SDP_VSC); > > intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, > @@ > > -2390,6 +2398,35 @@ void intel_psr_flush(struct drm_i915_private > > *dev_priv, > > } > > } > > > > +/** > > + * intel_panel_replay_init - Check for sink and source capability. > > + * @intel_dp: Intel DP > > + * > > + * This function is called after the initializing connector. > > + * (the initializing of connector treats the handling of connector > > +capabilities) > > + * And it initializes basic panel replay stuff for each DP Encoder. > > + */ > > +void intel_panel_replay_init(struct intel_dp *intel_dp) { > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > + u8 pr_dpcd = 0; > > + > > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv))) > > + return; > > + > > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, > > &pr_dpcd); > > + > > + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { > > + drm_dbg_kms(&dev_priv->drm, > > + "Panel replay is not supported by panel\n"); > > + return; > > + } > > + > > + drm_dbg_kms(&dev_priv->drm, > > + "Panel replay is supported by panel\n"); > > + intel_dp->psr.sink_panel_replay_support = true; } > > + > > /** > > * intel_psr_init - Init basic PSR work and mutex. > > * @intel_dp: Intel DP > > @@ -2404,7 +2441,7 @@ void intel_psr_init(struct intel_dp *intel_dp) > > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > > - if (!HAS_PSR(dev_priv)) > > + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) > > return; > > Should we continue initialization if PR is supported? > > > > > /* > > @@ -2423,6 +2460,7 @@ void intel_psr_init(struct intel_dp *intel_dp) > > } > > > > intel_dp->psr.source_support = true; > > + intel_dp->psr.source_panel_replay_support = true; Agree, this is little old code, setting of source_panel_replay_support flag would be under HAS_PANEL_REPLAY() check. Regards, Animesh > > > > /* Set link_standby x link_off defaults */ > > if (DISPLAY_VER(dev_priv) < 12) > > @@ -2432,6 +2470,8 @@ void intel_psr_init(struct intel_dp *intel_dp) > > INIT_WORK(&intel_dp->psr.work, intel_psr_work); > > INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, > > tgl_dc3co_disable_work); > > mutex_init(&intel_dp->psr.lock); > > + > > + intel_panel_replay_init(intel_dp); > > } > > > > static int psr_get_status_and_error_status(struct intel_dp *intel_dp, > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h > > b/drivers/gpu/drm/i915/display/intel_psr.h > > index 2ac3a46cccc5..38e613990418 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > > @@ -34,6 +34,7 @@ void intel_psr_flush(struct drm_i915_private > *dev_priv, > > unsigned frontbuffer_bits, > > enum fb_op_origin origin); > > void intel_psr_init(struct intel_dp *intel_dp); > > +void intel_panel_replay_init(struct intel_dp *intel_dp); > > void intel_psr_compute_config(struct intel_dp *intel_dp, > > struct intel_crtc_state *crtc_state, > > struct drm_connector_state *conn_state); > > -- > > 2.29.0
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8da87cbb172b..3c126bf47119 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1623,6 +1623,8 @@ struct intel_psr { bool irq_aux_error; u16 su_w_granularity; u16 su_y_granularity; + bool source_panel_replay_support; + bool sink_panel_replay_support; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; @@ -1926,6 +1928,11 @@ dp_to_lspcon(struct intel_dp *intel_dp) #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ (intel_dp)->psr.source_support) +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \ + (intel_dp)->psr.source_panel_replay_support) + +#define IS_PANEL_REPLAY(intel_dp) (!intel_dp_is_edp(intel_dp)) + static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { if (!intel_encoder_is_dp(encoder)) @@ -1934,6 +1941,14 @@ static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) return CAN_PSR(enc_to_intel_dp(encoder)); } +static inline bool intel_encoder_can_panel_replay(struct intel_encoder *encoder) +{ + if (!intel_encoder_is_dp(encoder)) + return false; + + return CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); +} + static inline struct intel_digital_port * hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7400d6b4c587..25bf18e40b96 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1726,12 +1726,23 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - /* - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ - * Colorimetry Format indication. - */ - vsc->revision = 0x5; + if (crtc_state->has_psr && conn_state->connector->connector_type != + DRM_MODE_CONNECTOR_eDP) { + /* + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel + * Encoding/Colorimetry Format indication. + */ + vsc->revision = 0x7; + } else { + /* + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ + * Colorimetry Format indication. + */ + vsc->revision = 0x5; + } + vsc->length = 0x13; /* DP 1.4a spec, Table 2-120 */ @@ -1840,6 +1851,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, vsc->revision = 0x4; vsc->length = 0xe; } + } else if (intel_dp->psr.enabled && IS_PANEL_REPLAY(intel_dp)) { + if (intel_dp->psr.colorimetry_support && + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { + /* [Panel Replay with colorimetry info] */ + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, + vsc); + } else { + /* + * [Panel Replay without colorimetry info] + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo + Panel Replay. + */ + vsc->revision = 0x6; + vsc->length = 0x10; + } } else { /* * [PSR1] @@ -3077,10 +3103,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ /* - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as - * per DP 1.4a spec. + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as + * per DP 1.4a spec and DP 2.0 spec respectively. */ - if (vsc->revision != 0x5) + if (vsc->revision != 0x5 || vsc->revision != 0x7) goto out; /* VSC SDP Payload for DB16 through DB18 */ diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a75b37851504..50394143c798 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -983,6 +983,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, &crtc_state->hw.adjusted_mode; int psr_setup_time; + if (CAN_PANEL_REPLAY(intel_dp)) + goto skip_psr_check; /* * Current PSR panels don't work reliably with VRR enabled * So if VRR is enabled, do not enable PSR. @@ -1026,8 +1028,14 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } +skip_psr_check: crtc_state->has_psr = true; - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); + + if (intel_dp_is_edp(intel_dp)) + crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); + + if (IS_PANEL_REPLAY(intel_dp) && HAS_PSR2_SEL_FETCH(dev_priv)) + crtc_state->has_psr2 = intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state, @@ -2390,6 +2398,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, } } +/** + * intel_panel_replay_init - Check for sink and source capability. + * @intel_dp: Intel DP + * + * This function is called after the initializing connector. + * (the initializing of connector treats the handling of connector capabilities) + * And it initializes basic panel replay stuff for each DP Encoder. + */ +void intel_panel_replay_init(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u8 pr_dpcd = 0; + + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv))) + return; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); + + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { + drm_dbg_kms(&dev_priv->drm, + "Panel replay is not supported by panel\n"); + return; + } + + drm_dbg_kms(&dev_priv->drm, + "Panel replay is supported by panel\n"); + intel_dp->psr.sink_panel_replay_support = true; +} + /** * intel_psr_init - Init basic PSR work and mutex. * @intel_dp: Intel DP @@ -2404,7 +2441,7 @@ void intel_psr_init(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (!HAS_PSR(dev_priv)) + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; /* @@ -2423,6 +2460,7 @@ void intel_psr_init(struct intel_dp *intel_dp) } intel_dp->psr.source_support = true; + intel_dp->psr.source_panel_replay_support = true; /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) @@ -2432,6 +2470,8 @@ void intel_psr_init(struct intel_dp *intel_dp) INIT_WORK(&intel_dp->psr.work, intel_psr_work); INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); mutex_init(&intel_dp->psr.lock); + + intel_panel_replay_init(intel_dp); } static int psr_get_status_and_error_status(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 2ac3a46cccc5..38e613990418 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -34,6 +34,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, unsigned frontbuffer_bits, enum fb_op_origin origin); void intel_psr_init(struct intel_dp *intel_dp); +void intel_panel_replay_init(struct intel_dp *intel_dp); void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state);
As panel replay feature similar to PSR feature of EDP panel, so currently utilized existing psr framework for panel replay. Cc: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- .../drm/i915/display/intel_display_types.h | 15 +++++++ drivers/gpu/drm/i915/display/intel_dp.c | 44 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_psr.c | 44 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_psr.h | 1 + 4 files changed, 93 insertions(+), 11 deletions(-)