diff mbox series

[05/10] drm/i915/dvo: Define a few more DVO register bits

Message ID 20221122120825.26338-6-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/dvo: Further DVO fixes/cleanups | expand

Commit Message

Ville Syrjälä Nov. 22, 2022, 12:08 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Define a few extra interrupt related bits on the DVO register.
One of these we included in the DVO_PRESERVE_MASK already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dvo.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
 2 files changed, 5 insertions(+), 2 deletions(-)

Comments

Jani Nikula Nov. 22, 2022, 12:33 p.m. UTC | #1 
On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define a few extra interrupt related bits on the DVO register.
> One of these we included in the DVO_PRESERVE_MASK already.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c | 3 ++-
>  drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index d20334d3394c..255deb55b932 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -290,7 +290,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
>  
>  	/* Save the data order, since I don't know what it should be set to. */
>  	dvo_val = intel_de_read(i915, DVO(port)) &
> -		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
> +		  (DVO_DEDICATED_INT_ENABLE |
> +		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
>  	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
>  		   DVO_BLANK_ACTIVE_HIGH;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5ae171eaee0..89c834d8fff8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2589,6 +2589,9 @@
>  #define   DVO_PIPE_STALL		(1 << 28)
>  #define   DVO_PIPE_STALL_TV		(2 << 28)
>  #define   DVO_PIPE_STALL_MASK		(3 << 28)
> +#define   DVO_INTERRUPT_SELECT		(1 << 27)
> +#define   DVO_DEDICATED_INT_ENABLE	(1 << 26)
> +#define   DVO_PRESERVE_MASK		(0x3 << 24)
>  #define   DVO_USE_VGA_SYNC		(1 << 15)
>  #define   DVO_DATA_ORDER_I740		(0 << 14)
>  #define   DVO_DATA_ORDER_FP		(1 << 14)
> @@ -2606,7 +2609,6 @@
>  #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
>  #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
>  #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
> -#define   DVO_PRESERVE_MASK		(0x7 << 24)
>  #define _DVOA_SRCDIM		0x61124
>  #define _DVOB_SRCDIM		0x61144
>  #define _DVOC_SRCDIM		0x61164
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index d20334d3394c..255deb55b932 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -290,7 +290,8 @@  static void intel_dvo_pre_enable(struct intel_atomic_state *state,
 
 	/* Save the data order, since I don't know what it should be set to. */
 	dvo_val = intel_de_read(i915, DVO(port)) &
-		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
+		  (DVO_DEDICATED_INT_ENABLE |
+		   DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
 	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
 		   DVO_BLANK_ACTIVE_HIGH;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5ae171eaee0..89c834d8fff8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2589,6 +2589,9 @@ 
 #define   DVO_PIPE_STALL		(1 << 28)
 #define   DVO_PIPE_STALL_TV		(2 << 28)
 #define   DVO_PIPE_STALL_MASK		(3 << 28)
+#define   DVO_INTERRUPT_SELECT		(1 << 27)
+#define   DVO_DEDICATED_INT_ENABLE	(1 << 26)
+#define   DVO_PRESERVE_MASK		(0x3 << 24)
 #define   DVO_USE_VGA_SYNC		(1 << 15)
 #define   DVO_DATA_ORDER_I740		(0 << 14)
 #define   DVO_DATA_ORDER_FP		(1 << 14)
@@ -2606,7 +2609,6 @@ 
 #define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
 #define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
-#define   DVO_PRESERVE_MASK		(0x7 << 24)
 #define _DVOA_SRCDIM		0x61124
 #define _DVOB_SRCDIM		0x61144
 #define _DVOC_SRCDIM		0x61164