| Message ID | 20221125173156.31689-8-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Fake dual eDP VBT fixes | expand |
> -----Original Message----- > From: Ville Syrjala <ville.syrjala@linux.intel.com> > Sent: Friday, November 25, 2022 11:02 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh <animesh.manna@intel.com> > Subject: [PATCH v2 7/9] drm/i915: Print the PPS registers using consistent > format > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Use the consistent format when dumping out the PPS control/status > registers. Helps with pattern matching. > > Cc: Animesh Manna <animesh.manna@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_pps.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c > b/drivers/gpu/drm/i915/display/intel_pps.c > index d18c1c58dfcf..f6bc896338de 100644 > --- a/drivers/gpu/drm/i915/display/intel_pps.c > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > @@ -527,7 +527,8 @@ void intel_pps_check_power_unlocked(struct > intel_dp *intel_dp) > if (!edp_have_panel_power(intel_dp) && > !edp_have_panel_vdd(intel_dp)) { > drm_WARN(&dev_priv->drm, 1, > "eDP powered off while attempting aux channel > communication.\n"); > - drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control > 0x%08x\n", > + drm_dbg_kms(&dev_priv->drm, > + "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", > intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), > intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); > } > @@ -559,7 +560,7 @@ static void wait_panel_status(struct intel_dp > *intel_dp, > pp_ctrl_reg = _pp_ctrl_reg(intel_dp); > > drm_dbg_kms(&dev_priv->drm, > - "mask %08x value %08x status %08x control %08x\n", > + "mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x > PP_CONTROL: > +0x%08x\n", > mask, value, > intel_de_read(dev_priv, pp_stat_reg), > intel_de_read(dev_priv, pp_ctrl_reg)); @@ -567,7 +568,7 > @@ static void wait_panel_status(struct intel_dp *intel_dp, > if (intel_de_wait_for_register(dev_priv, pp_stat_reg, > mask, value, 5000)) > drm_err(&dev_priv->drm, > - "Panel status timeout: status %08x control %08x\n", > + "Panel status timeout: PP_STATUS: 0x%08x > PP_CONTROL: 0x%08x\n", > intel_de_read(dev_priv, pp_stat_reg), > intel_de_read(dev_priv, pp_ctrl_reg)); > > -- > 2.37.4
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index d18c1c58dfcf..f6bc896338de 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -527,7 +527,8 @@ void intel_pps_check_power_unlocked(struct intel_dp *intel_dp) if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { drm_WARN(&dev_priv->drm, 1, "eDP powered off while attempting aux channel communication.\n"); - drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", + drm_dbg_kms(&dev_priv->drm, + "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); } @@ -559,7 +560,7 @@ static void wait_panel_status(struct intel_dp *intel_dp, pp_ctrl_reg = _pp_ctrl_reg(intel_dp); drm_dbg_kms(&dev_priv->drm, - "mask %08x value %08x status %08x control %08x\n", + "mask: 0x%08x value: 0x%08x PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg)); @@ -567,7 +568,7 @@ static void wait_panel_status(struct intel_dp *intel_dp, if (intel_de_wait_for_register(dev_priv, pp_stat_reg, mask, value, 5000)) drm_err(&dev_priv->drm, - "Panel status timeout: status %08x control %08x\n", + "Panel status timeout: PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg));