@@ -848,24 +848,34 @@ dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
}
static bool
-ycbcr420_scaler_constraints(const struct drm_display_mode *mode)
+ycbcr420_constraints(const struct drm_display_mode *mode, bool with_dsc)
{
+ /*
+ * DSC with YCbCr420 is a constraint as currently we do not support compression
+ * with 420 format.
+ */
+ if (with_dsc)
+ return true;
+
return mode->hdisplay > 4096 || mode->vdisplay > 5120;
}
static enum intel_output_format
intel_dp_output_format(struct intel_connector *connector,
const struct drm_display_mode *mode,
- enum intel_output_format sink_format)
+ enum intel_output_format sink_format,
+ bool with_dsc)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
/*
* For YCbCr420 output, scaler is required for downsampling.
- * So go for native YCbCr420 only if there are no scaler constraints.
+ * DSC1.1 supports compression only with 444 formats.
+ * So go for native YCbCr420 only if there are no scaler and dsc constraints.
*/
- if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 || !ycbcr420_scaler_constraints(mode)) &&
- source_can_output(intel_dp, sink_format))
+ if (source_can_output(intel_dp, sink_format) &&
+ (sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 ||
+ !ycbcr420_constraints(mode, with_dsc)))
return sink_format;
if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
@@ -912,7 +922,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector,
else
sink_format = INTEL_OUTPUT_FORMAT_RGB;
- output_format = intel_dp_output_format(connector, mode, sink_format);
+ output_format = intel_dp_output_format(connector, mode, sink_format, false);
return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
}
@@ -1661,7 +1671,8 @@ static int
intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+ bool respect_downstream_limits,
+ bool with_dsc)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -1672,6 +1683,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool joiner_needs_dsc = false;
int ret;
+ if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
+ adjusted_mode->crtc_clock))
+ pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
+
+ /*
+ * Pipe joiner needs compression up to display 12 due to bandwidth
+ * limitation. DG2 onwards pipe joiner can be enabled without
+ * compression.
+ */
+ joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
+
+ if (joiner_needs_dsc && !with_dsc)
+ return -EINVAL;
+
limits.min_rate = intel_dp_common_rate(intel_dp, 0);
limits.max_rate = intel_dp_max_link_rate(intel_dp);
@@ -1701,23 +1726,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
limits.max_lane_count, limits.max_rate,
limits.max_bpp, adjusted_mode->crtc_clock);
- if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
- adjusted_mode->crtc_clock))
- pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
-
- /*
- * Pipe joiner needs compression up to display 12 due to bandwidth
- * limitation. DG2 onwards pipe joiner can be enabled without
- * compression.
- */
- joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
-
/*
* Optimize for slow and wide for everything, because there are some
* eDP 1.3 and 1.4 panels don't work well with fast and narrow.
*/
ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
+ if (ret && !with_dsc)
+ return -EINVAL;
+
if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
@@ -2053,7 +2070,8 @@ static int
intel_dp_compute_output_format(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+ bool respect_downstream_limits,
+ bool with_dsc)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2076,10 +2094,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
}
crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode,
- crtc_state->sink_format);
+ crtc_state->sink_format, with_dsc);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
- respect_downstream_limits);
+ respect_downstream_limits, with_dsc);
if (ret) {
if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
!drm_mode_is_420_also(info, adjusted_mode))
@@ -2087,9 +2105,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode,
- crtc_state->sink_format);
+ crtc_state->sink_format,
+ with_dsc);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
- respect_downstream_limits);
+ respect_downstream_limits, with_dsc);
}
return ret;
@@ -2136,9 +2155,21 @@ intel_dp_compute_config(struct intel_encoder *encoder,
* Try to respect downstream TMDS clock limits first, if
* that fails assume the user might know something we don't.
*/
- ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, true, false);
if (ret)
- ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, false, false);
+
+ /* Try with DSC */
+ if (ret) {
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, true, true);
+ if (ret)
+ ret = intel_dp_compute_output_format(encoder, pipe_config,
+ conn_state, false, true);
+ }
+
if (ret)
return ret;
Currently we compute the output format first and later try DSC if the bandwidth without compression is not sufficient for that output format. Since we do not support DSC with YCbCr420 format, this creates problem for YCbCr420 only modes, that can be still be set if DFP has color conversion and DSC capabilities. So compute output format, first without DSC and inturn compute the link config without DSC. If cannot be supported without DSC, compute the output format with DSC and continue. With this apporach, check can be added for YCbCr420 output, which cannot be supported with DSC. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 81 +++++++++++++++++-------- 1 file changed, 56 insertions(+), 25 deletions(-)