From patchwork Mon Nov 28 10:19:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13057239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9055C4167D for ; Mon, 28 Nov 2022 10:19:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA7E410E0F0; Mon, 28 Nov 2022 10:19:27 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id D58F410E2C7 for ; Mon, 28 Nov 2022 10:18:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669630721; x=1701166721; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZS9X60tYMejewTKJkG4Cd6cNM15FI1uSxzl87a8nGG0=; b=SAe869wCQpk2zO97vOFjhzpC97BhZAln5bAusoiZCLpnfUTOfzzAg4Ll +rVTabx/l+10f2yU1Jz930hPXPe6xAEh/wfc1nbb0Bv0oeVna9VSqjXfa g0ROQlWnJksbPbOTERQMpQNSOpfrvBY00DQEaJOCMQfIDComVMoSfpH4d jWu9MKzJ0Gh0uCFj3ck+q6gjSCoz+g74WSdDkKjAjRSWYGobygiHNfJXB Aealndeu854tRlE089Uxh+TnJy8S+IR25A8Pwnwg4zpkEj53KJH4qleQY +DAsbMoOognTQlLuXlXr+lwTp3oGdYL3c1qpjHaY+n6tRl7hTQ6NRqHnJ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="294500142" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="294500142" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 02:18:41 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10544"; a="749319797" X-IronPort-AV: E=Sophos;i="5.96,200,1665471600"; d="scan'208";a="749319797" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2022 02:18:39 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 28 Nov 2022 15:49:18 +0530 Message-Id: <20221128101922.217217-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221128101922.217217-1-ankit.k.nautiyal@intel.com> References: <20221128101922.217217-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/11] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate the precision during calculation of transfer unit data for hblank_early calculation. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_audio.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index f63d5824aca2..4797040a6362 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -510,14 +510,14 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, unsigned int link_clks_available, link_clks_required; unsigned int tu_data, tu_line, link_clks_active; unsigned int h_active, h_total, hblank_delta, pixel_clk; - unsigned int fec_coeff, cdclk, vdsc_bpp; + unsigned int fec_coeff, cdclk, vdsc_bppx16; unsigned int link_clk, lanes; unsigned int hblank_rise; h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; - vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); + vdsc_bppx16 = crtc_state->dsc.compressed_bpp; cdclk = i915->display.cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 1000000 */ fec_coeff = 972261; @@ -525,10 +525,10 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, lanes = crtc_state->lane_count; drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :" - "lanes = %u vdsc_bpp = %u cdclk = %u\n", - h_active, link_clk, lanes, vdsc_bpp, cdclk); + "lanes = %u vdsc_bppx16 = %u cdclk = %u\n", + h_active, link_clk, lanes, vdsc_bppx16, cdclk); - if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) + if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) return 0; link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; @@ -540,7 +540,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), mul_u32_u32(link_clk, cdclk)); - tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), + tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 16 * 1000000), mul_u32_u32(link_clk * lanes, fec_coeff)); tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), mul_u32_u32(64 * pixel_clk, 1000000));