| Message ID | 20221212070228.2563936-1-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled | expand |
Hi Mitul,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Mitul-Golani/drm-i915-display-Enable-VDIP-Enable-VSC-whenever-GMP-DIP-enabled/20221212-150320
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20221212070228.2563936-1-mitulkumar.ajitkumar.golani%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled
config: x86_64-rhel-8.3-syz
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/fd314da00de92f1e6f044aac7082e23366482e5c
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Mitul-Golani/drm-i915-display-Enable-VDIP-Enable-VSC-whenever-GMP-DIP-enabled/20221212-150320
git checkout fd314da00de92f1e6f044aac7082e23366482e5c
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_dp.c: In function 'intel_dp_set_infoframes':
drivers/gpu/drm/i915/display/intel_dp.c:3282:25: error: expected ')' before 'dip_enable'
3282 | dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW;
| ^~~~~~~~~~
drivers/gpu/drm/i915/display/intel_dp.c:3281:12: note: to match this '('
3281 | if (IS_DISPLAY_VER(dev_priv, 13, 14)
| ^
drivers/gpu/drm/i915/display/intel_dp.c:3301:1: error: expected expression before '}' token
3301 | }
| ^
>> drivers/gpu/drm/i915/display/intel_dp.c:3278:13: error: unused variable 'dip_enable' [-Werror=unused-variable]
3278 | u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
| ^~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_dp.c:3277:20: error: unused variable 'reg' [-Werror=unused-variable]
3277 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
| ^~~
At top level:
>> drivers/gpu/drm/i915/display/intel_dp.c:3219:13: error: 'intel_write_dp_sdp' defined but not used [-Werror=unused-function]
3219 | static void intel_write_dp_sdp(struct intel_encoder *encoder,
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/dip_enable +3278 drivers/gpu/drm/i915/display/intel_dp.c
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3218
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 @3219 static void intel_write_dp_sdp(struct intel_encoder *encoder,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3220 const struct intel_crtc_state *crtc_state,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3221 unsigned int type)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3222 {
7801f3b792b0fd Lucas De Marchi 2020-06-30 3223 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3225 struct dp_sdp sdp = {};
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3226 ssize_t len;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3227
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3228 if ((crtc_state->infoframes.enable &
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3229 intel_hdmi_infoframe_enable(type)) == 0)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3230 return;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3231
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3232 switch (type) {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3233 case DP_SDP_VSC:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3234 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3235 sizeof(sdp));
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3236 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3237 case HDMI_PACKET_TYPE_GAMUT_METADATA:
9d0bfa7ac97c62 Jani Nikula 2022-01-21 3238 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
9d0bfa7ac97c62 Jani Nikula 2022-01-21 3239 &crtc_state->infoframes.drm.drm,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3240 &sdp, sizeof(sdp));
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3241 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3242 default:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3243 MISSING_CASE(type);
d121f63c00e3b8 Chris Wilson 2020-03-25 3244 return;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3245 }
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3246
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3247 if (drm_WARN_ON(&dev_priv->drm, len < 0))
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3248 return;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3249
7801f3b792b0fd Lucas De Marchi 2020-06-30 3250 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3251 }
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3252
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3253 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3254 const struct intel_crtc_state *crtc_state,
9ce5884e513903 José Roberto de Souza 2021-09-22 3255 const struct drm_dp_vsc_sdp *vsc)
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3256 {
7801f3b792b0fd Lucas De Marchi 2020-06-30 3257 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3259 struct dp_sdp sdp = {};
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3260 ssize_t len;
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3261
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3262 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3263
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3264 if (drm_WARN_ON(&dev_priv->drm, len < 0))
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3265 return;
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3266
7801f3b792b0fd Lucas De Marchi 2020-06-30 3267 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3268 &sdp, len);
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3269 }
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3270
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3271 void intel_dp_set_infoframes(struct intel_encoder *encoder,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3272 bool enable,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3273 const struct intel_crtc_state *crtc_state,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3274 const struct drm_connector_state *conn_state)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3275 {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3276 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 @3277 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 @3278 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3279 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3280 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
fd314da00de92f Mitul Golani 2022-12-12 @3281 if (IS_DISPLAY_VER(dev_priv, 13, 14)
fd314da00de92f Mitul Golani 2022-12-12 @3282 dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW;
62e37c44a58e62 José Roberto de Souza 2021-04-17 3283 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3284
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3285 /* TODO: Add DSC case (DIP_ENABLE_PPS) */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3286 /* When PSR is enabled, this routine doesn't disable VSC DIP */
62e37c44a58e62 José Roberto de Souza 2021-04-17 3287 if (!crtc_state->has_psr)
62e37c44a58e62 José Roberto de Souza 2021-04-17 3288 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3289
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3290 intel_de_write(dev_priv, reg, val);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3291 intel_de_posting_read(dev_priv, reg);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3292
62e37c44a58e62 José Roberto de Souza 2021-04-17 3293 if (!enable)
62e37c44a58e62 José Roberto de Souza 2021-04-17 3294 return;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3295
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3296 /* When PSR is enabled, VSC SDP is handled by PSR routine */
d54e017e62d806 José Roberto de Souza 2021-04-17 3297 if (!crtc_state->has_psr)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3298 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3299
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3300 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3301 }
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3302
On Mon, 12 Dec 2022, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote: > GMP VDIP gets dropped when enabled without VSC DIP being > enabled. Enable VSC DIP whenever GMP DIP is enabled I saw the fixed version, but for future reference, please run checkpatch locally and use CONFIG_DRM_I915_WERROR=y for i915 development to catch simple errors before sending the patches. Thanks, Jani. > > WA:14015402699 > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ > drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 72cf83a27405..4d63a9ce5f42 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -3278,6 +3278,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, > u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | > VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | > VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; > + if (IS_DISPLAY_VER(dev_priv, 13, 14) > + dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW; > u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; > > /* TODO: Add DSC case (DIP_ENABLE_PPS) */ > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c > index 9ff1c0b223ad..a5c449a05b4d 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > @@ -630,6 +630,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > tmp = intel_de_read(dev_priv, > HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); > mask = VIDEO_DIP_ENABLE_GMP_HSW; > + if (IS_DISPLAY_VER(dev_priv, 13, 14) > + mask |= VIDEO_DIP_ENABLE_VSC_HSW; > > if (tmp & mask) > val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 72cf83a27405..4d63a9ce5f42 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3278,6 +3278,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; + if (IS_DISPLAY_VER(dev_priv, 13, 14) + dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW; u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; /* TODO: Add DSC case (DIP_ENABLE_PPS) */ diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 9ff1c0b223ad..a5c449a05b4d 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -630,6 +630,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, tmp = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); mask = VIDEO_DIP_ENABLE_GMP_HSW; + if (IS_DISPLAY_VER(dev_priv, 13, 14) + mask |= VIDEO_DIP_ENABLE_VSC_HSW; if (tmp & mask) val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
GMP VDIP gets dropped when enabled without VSC DIP being enabled. Enable VSC DIP whenever GMP DIP is enabled WA:14015402699 Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++ 2 files changed, 4 insertions(+)