diff mbox series

drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled

Message ID 20221212073325.2678764-1-mitulkumar.ajitkumar.golani@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/display: Enable VDIP Enable VSC whenever GMP DIP enabled | expand

Commit Message

Golani, Mitulkumar Ajitkumar Dec. 12, 2022, 7:33 a.m. UTC 
GMP VDIP gets dropped when enabled without VSC DIP being
enabled. Enable VSC DIP whenever GMP DIP is enabled

WA:14015402699

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 5 ++++-
 drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

Comments

Ville Syrjälä Dec. 13, 2022, 2:58 a.m. UTC | #1 
On Mon, Dec 12, 2022 at 01:03:25PM +0530, Mitul Golani wrote:
> GMP VDIP gets dropped when enabled without VSC DIP being
> enabled. Enable VSC DIP whenever GMP DIP is enabled
> 
> WA:14015402699
> 
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 5 ++++-
>  drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++
>  2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 72cf83a27405..6c36ee26d399 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3275,10 +3275,13 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
> +	u32 val;
>  	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
>  			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
>  			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
> -	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
> +	if (IS_DISPLAY_VER(dev_priv, 13, 14))
> +		dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW;

What kind of garbage are we going to be sending to the sink here?

> +	val = intel_de_read(dev_priv, reg) & ~dip_enable;
>  
>  	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
>  	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
> index 9ff1c0b223ad..e7cdc521fbd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> @@ -630,6 +630,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
>  		tmp = intel_de_read(dev_priv,
>  				    HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
>  		mask = VIDEO_DIP_ENABLE_GMP_HSW;
> +		if (IS_DISPLAY_VER(dev_priv, 13, 14))
> +			mask |= VIDEO_DIP_ENABLE_VSC_HSW;
>  
>  		if (tmp & mask)
>  			val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> -- 
> 2.25.1
Golani, Mitulkumar Ajitkumar Dec. 13, 2022, 2:55 p.m. UTC | #2 
Hi Ville

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: 13 December 2022 08:28
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Enable VDIP Enable VSC
> whenever GMP DIP enabled
> 
> On Mon, Dec 12, 2022 at 01:03:25PM +0530, Mitul Golani wrote:
> > GMP VDIP gets dropped when enabled without VSC DIP being enabled.
> > Enable VSC DIP whenever GMP DIP is enabled
> >
> > WA:14015402699
> >
> > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c     | 5 ++++-
> >  drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++
> >  2 files changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 72cf83a27405..6c36ee26d399 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -3275,10 +3275,13 @@ void intel_dp_set_infoframes(struct
> > intel_encoder *encoder,  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
> > +	u32 val;
> >  	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
> VIDEO_DIP_ENABLE_GCP_HSW |
> >  			 VIDEO_DIP_ENABLE_VS_HSW |
> VIDEO_DIP_ENABLE_GMP_HSW |
> >  			 VIDEO_DIP_ENABLE_SPD_HSW |
> VIDEO_DIP_ENABLE_DRM_GLK;
> > -	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
> > +	if (IS_DISPLAY_VER(dev_priv, 13, 14))
> > +		dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW;
> 
> What kind of garbage are we going to be sending to the sink here?
As suggested by the Workaround: 14015405644 GMP VDIP is dropped
when enabled without VSC VDIP. 

As part of this Workaround implementation, enabled VSC DIP whenever
GMP DIP is enabled.

Regards,
Mitul
> > +	val = intel_de_read(dev_priv, reg) & ~dip_enable;
> >
> >  	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
> >  	/* When PSR is enabled, this routine doesn't disable VSC DIP */ diff
> > --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > index 9ff1c0b223ad..e7cdc521fbd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
> > @@ -630,6 +630,8 @@ u32 lspcon_infoframes_enabled(struct
> intel_encoder *encoder,
> >  		tmp = intel_de_read(dev_priv,
> >  				    HSW_TVIDEO_DIP_CTL(pipe_config-
> >cpu_transcoder));
> >  		mask = VIDEO_DIP_ENABLE_GMP_HSW;
> > +		if (IS_DISPLAY_VER(dev_priv, 13, 14))
> > +			mask |= VIDEO_DIP_ENABLE_VSC_HSW;
> >
> >  		if (tmp & mask)
> >  			val |=
> > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
> > --
> > 2.25.1
> 
> --
> Ville Syrjälä
> Intel
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 72cf83a27405..6c36ee26d399 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3275,10 +3275,13 @@  void intel_dp_set_infoframes(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+	u32 val;
 	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
 			 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
-	u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+	if (IS_DISPLAY_VER(dev_priv, 13, 14))
+		dip_enable |= VIDEO_DIP_ENABLE_VSC_HSW;
+	val = intel_de_read(dev_priv, reg) & ~dip_enable;
 
 	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
 	/* When PSR is enabled, this routine doesn't disable VSC DIP */
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index 9ff1c0b223ad..e7cdc521fbd3 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -630,6 +630,8 @@  u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
 		tmp = intel_de_read(dev_priv,
 				    HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 		mask = VIDEO_DIP_ENABLE_GMP_HSW;
+		if (IS_DISPLAY_VER(dev_priv, 13, 14))
+			mask |= VIDEO_DIP_ENABLE_VSC_HSW;
 
 		if (tmp & mask)
 			val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);