From patchwork Tue Dec 13 12:39:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 13072027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0215C4332F for ; Tue, 13 Dec 2022 12:39:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BD8A10E1D7; Tue, 13 Dec 2022 12:39:36 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A07510E1C3; Tue, 13 Dec 2022 12:39:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670935168; x=1702471168; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=k7I6Dcl2sKHyS9GgzEXDkKJ0s/zPJV0OhvB6MFSO7zU=; b=O9w3eTOr/xcl64xgsMbTgT+CAoqtH5Hb0VQLNjc37SPWJnoRQnxDyap6 1FvcveEnyp373oB6fmKCKHwK2skcimPxF7B+6NHDXjTwUcr5+gjlqQ/LV cm0G3Ltpcy6PRvKx4luYK/Y4xGhu0RvNcjVME8R22f/lnbkCKeXyeOiik Ax9cx97BRtB7wWVPNwuvmrC+LVWpe1bKqYmuW321TQDW7wWpJI9w75lLV qA5IES1XDrfO85m6L77EDfq2Pfun3GjUpu2NdTSlsrEmu3FdAw+q4zz7I J189V1CKHtvbZT0owbbGdyM7yTUJF8fU+amIOdo+Ks6Hnh1GDxSXjv0uh w==; X-IronPort-AV: E=McAfee;i="6500,9779,10559"; a="316822400" X-IronPort-AV: E=Sophos;i="5.96,241,1665471600"; d="scan'208";a="316822400" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 04:39:28 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10559"; a="737375482" X-IronPort-AV: E=Sophos;i="5.96,241,1665471600"; d="scan'208";a="737375482" Received: from lherman-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.213.234.101]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2022 04:39:26 -0800 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Tue, 13 Dec 2022 12:39:16 +0000 Message-Id: <20221213123917.4066375-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: fix TLB invalidation for Gen12.50 video and compute engines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Hajda Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andrzej Hajda In case of Gen12.50 video and compute engines, TLB_INV registers are masked - to modify one bit, corresponding bit in upper half of the register must be enabled, otherwise nothing happens. Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers") Signed-off-by: Andrzej Hajda Reviewed-by: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 63f95c5f3614..7eeee5a7cb33 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -1100,9 +1100,15 @@ static void mmio_invalidate_full(struct intel_gt *gt) continue; if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { + u32 val = BIT(engine->instance); + + if (engine->class == VIDEO_DECODE_CLASS || + engine->class == VIDEO_ENHANCEMENT_CLASS || + engine->class == COMPUTE_CLASS) + val = _MASKED_BIT_ENABLE(val); intel_gt_mcr_multicast_write_fw(gt, xehp_regs[engine->class], - BIT(engine->instance)); + val); } else { rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); if (!i915_mmio_reg_offset(rb.reg))