@@ -14,6 +14,8 @@
#include "gt/intel_gt_regs.h"
+#include "gt/uc/intel_gsc_fw.h"
+
#include "i915_drv.h"
#include "i915_file_private.h"
#include "i915_gpu_error.h"
@@ -668,6 +670,64 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
return NULL;
}
+static int __reset_guc(struct intel_gt *gt)
+{
+ u32 guc_domain =
+ GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
+
+ return gen6_hw_domain_reset(gt, guc_domain);
+}
+
+static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
+{
+ if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
+ return false;
+
+ if (!__HAS_ENGINE(engine_mask, GSC0))
+ return false;
+
+ return intel_gsc_uc_fw_init_done(>->uc.gsc);
+}
+
+static intel_engine_mask_t
+wa_14015076503_start(struct intel_gt *gt, intel_engine_mask_t engine_mask, bool first)
+{
+ if (!needs_wa_14015076503(gt, engine_mask))
+ return engine_mask;
+
+ /*
+ * wa_14015076503: if the GSC FW is loaded, we need to alert it that
+ * we're going to do a GSC engine reset and then wait for 200ms for the
+ * FW to get ready for it. However, if this the first ALL_ENGINES reset
+ * attempt and the GSC is not busy, we can try to instead reset the GuC
+ * and all the other engines individually to avoid the 200ms wait.
+ */
+ if (engine_mask == ALL_ENGINES && first && intel_engine_is_idle(gt->engine[GSC0])) {
+ __reset_guc(gt);
+ engine_mask = gt->info.engine_mask & ~BIT(GSC0);
+ } else {
+ intel_uncore_write(gt->uncore,
+ HECI_GENERAL_STATUS(MTL_GSC_HECI2_BASE),
+ BIT(0));
+ intel_uncore_write(gt->uncore,
+ HECI_CONTROL_AND_STATUS(MTL_GSC_HECI2_BASE),
+ BIT(2));
+ msleep(200);
+ }
+
+ return engine_mask;
+}
+
+static void
+wa_14015076503_end(struct intel_gt *gt, intel_engine_mask_t engine_mask)
+{
+ if (!needs_wa_14015076503(gt, engine_mask))
+ return;
+
+ intel_uncore_write(gt->uncore,
+ HECI_GENERAL_STATUS(MTL_GSC_HECI2_BASE), 0);
+}
+
int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
@@ -685,10 +745,16 @@ int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
*/
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
- GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
+ intel_engine_mask_t reset_mask;
+
+ reset_mask = wa_14015076503_start(gt, engine_mask, !retry);
+
+ GT_TRACE(gt, "engine_mask=%x\n", reset_mask);
preempt_disable();
- ret = reset(gt, engine_mask, retry);
+ ret = reset(gt, reset_mask, retry);
preempt_enable();
+
+ wa_14015076503_end(gt, reset_mask);
}
intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
@@ -713,14 +779,12 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
int intel_reset_guc(struct intel_gt *gt)
{
- u32 guc_domain =
- GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
int ret;
GEM_BUG_ON(!HAS_GT_UC(gt->i915));
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
- ret = gen6_hw_domain_reset(gt, guc_domain);
+ ret = __reset_guc(gt);
intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
return ret;
@@ -923,8 +923,11 @@
#define DG1_GSC_HECI2_BASE 0x00259000
#define DG2_GSC_HECI1_BASE 0x00373000
#define DG2_GSC_HECI2_BASE 0x00374000
+#define MTL_GSC_HECI1_BASE 0x00116000
+#define MTL_GSC_HECI2_BASE 0x00117000
-
+#define HECI_CONTROL_AND_STATUS(base) _MMIO(base + 0x4)
+#define HECI_GENERAL_STATUS(base) _MMIO(base + 0xc4c)
#define HSW_GTT_CACHE_EN _MMIO(0x4024)
#define GTT_CACHE_EN_ALL 0xF0007FFF
The WA states that before doing a GSC engine reset we need to alert the GSC FW and then wait for 200ms for the FW to get ready for it. The GuC will take care of this for engine reset, but i915 is still responsible for the full GT reset scenario. Given that we do full GT resets in the resume paths to cleanup the HW state and that waiting 200ms in those scenarios would not be acceptable, a faster path has been introduced where, if there are no pending submissions to the GSC engine, we first try to individually reset the GuC and all engines except the GSC and only fall back to full reset if that fails. Note that the 200ms wait is based on the worst case scenario and it should be possible to limit the wait to a shorter time if the GSC FW is idle when we alert it. However, the GSC FW team has advised against this approach as the shorter wait time in that case would depend on the actual power state of the microcontroller, because suspend exit time might have to be added in. The GSC engine is very rarely active anyway, so we should take the faster path in the great majority of cases. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: John Harrison <john.c.harrison@intel.com> --- drivers/gpu/drm/i915/gt/intel_reset.c | 74 +++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 5 +- 2 files changed, 73 insertions(+), 6 deletions(-)