From patchwork Thu Jan 12 09:27:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaitanya Kumar Borah X-Patchwork-Id: 13097717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7407C54EBD for ; Thu, 12 Jan 2023 09:28:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CF4110E8B7; Thu, 12 Jan 2023 09:28:36 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 84E6110E8B7 for ; Thu, 12 Jan 2023 09:28:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673515712; x=1705051712; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WpI/TKkS3zwWEsH9TuG78zltxnTTM6D+YvcGYzXXnrk=; b=FpAoSWspG0FxJAh4KfUnTklOp7S2rQjCTLm24Vv54wC/Kq2HtVSIkyh2 QZK/XIbDY15quD112siTB9lesm39hNY9ZQj5zBlHFfjWjQZY/Mjp4wtRf zMm/iulBZGvtmKgugS4kyJh/FpXFbl48HC+D+l55wSgM0uNOEu1MNXODw WuvA+6zgSG4+a1Bo78HwmqB5lNp3KNipNhLNqOvdwOMiPZ8sFGbzj66WJ cLMS9Ub3hVnpTLjlcSJtP4/llFj1hIEzhSO/VaiKFb00z1ifTrCkYdvqA ukuZF6LqhCtOgZ9CvQ3i/oMywpSob8sxAOr/57m1oeD/B4nuNpg1CsAy1 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307178139" X-IronPort-AV: E=Sophos;i="5.96,319,1665471600"; d="scan'208";a="307178139" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 01:28:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831627530" X-IronPort-AV: E=Sophos;i="5.96,319,1665471600"; d="scan'208";a="831627530" Received: from chaitanya.iind.intel.com ([10.190.239.113]) by orsmga005.jf.intel.com with ESMTP; 12 Jan 2023 01:28:15 -0800 From: Chaitanya Kumar Borah To: intel-gfx@lists.freedesktop.org Date: Thu, 12 Jan 2023 14:57:58 +0530 Message-Id: <20230112092758.539070-3-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230112092758.539070-1-chaitanya.kumar.borah@intel.com> References: <20230112092758.539070-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A new step of 480MHz has been added on SKUs that have a RPL-U device id to support 120Hz displays more efficiently. Use a new quirk to identify the machine for which this change needs to be applied. BSpec: 55409 v2: (Matt) - Add missing clock steps - Correct reference clock typo Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 0c107a38f9d0..ba365ef17abc 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals rplu_cdclk_table[] = { + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, + { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 }, + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, + + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, + { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 }, + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, + { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, + + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 }, + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, + {} +}; + static const struct intel_cdclk_vals dg2_cdclk_table[] = { { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, @@ -3353,6 +3377,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) /* Wa_22011320316:adl-p[a0] */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; + else if (IS_ADLP_WITH_480CDCLK(dev_priv)) + dev_priv->display.cdclk.table = rplu_cdclk_table; else dev_priv->display.cdclk.table = adlp_cdclk_table; } else if (IS_ROCKETLAKE(dev_priv)) {