| Message ID | 20230113130628.19772-1-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Implement UHBR bandwidth check | expand |
On Fri, Jan 13, 2023 at 03:06:28PM +0200, Stanislav Lisovskiy wrote: > According to spec, we should check if output_bpp * pixel_rate is less > than DDI clock * 72, if UHBR is used. > > HSDES: 1406899791 > BSPEC: 49259 > > v2: - Removed wrong comment(Rodrigo Vivi) > - Added HSDES to the commit msg(Rodrigo Vivi) > - Moved UHBR check to the MST specific code > > v3: - Changed commit subject(Rodrigo Vivi) > - Fixed the error message if check fails(Rodrigo Vivi) > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 8b0e4defa3f1..36e368995bef 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -339,10 +339,20 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, > ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, > conn_state, &limits, > pipe_config->dp_m_n.tu, false); > - } > + if (ret < 0) > + return ret; > > - if (ret) > - return ret; > + if (intel_dp_is_uhbr(pipe_config)) { > + int output_bpp = pipe_config->dsc.compressed_bpp; > + > + if (output_bpp * adjusted_mode->crtc_clock >= > + pipe_config->port_clock * 72) { > + drm_dbg_kms(&dev_priv->drm, "UHBR check failed(required bw %d available %d)\n", > + output_bpp * adjusted_mode->crtc_clock, pipe_config->port_clock * 72); > + return -EINVAL; Doesn't this just mean the user can never enable this particular mode? Would seem more sensible to account for the extra limitation when we determine port_clock and/or compressed_bpp. > + } > + } > + } > > ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state); > if (ret) > -- > 2.37.3
On Fri, Jan 13, 2023 at 04:43:54PM +0200, Ville Syrjälä wrote: > On Fri, Jan 13, 2023 at 03:06:28PM +0200, Stanislav Lisovskiy wrote: > > According to spec, we should check if output_bpp * pixel_rate is less > > than DDI clock * 72, if UHBR is used. > > > > HSDES: 1406899791 > > BSPEC: 49259 > > > > v2: - Removed wrong comment(Rodrigo Vivi) > > - Added HSDES to the commit msg(Rodrigo Vivi) > > - Moved UHBR check to the MST specific code > > > > v3: - Changed commit subject(Rodrigo Vivi) > > - Fixed the error message if check fails(Rodrigo Vivi) > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++--- > > 1 file changed, 13 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index 8b0e4defa3f1..36e368995bef 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -339,10 +339,20 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, > > ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, > > conn_state, &limits, > > pipe_config->dp_m_n.tu, false); > > - } > > + if (ret < 0) > > + return ret; > > > > - if (ret) > > - return ret; > > + if (intel_dp_is_uhbr(pipe_config)) { > > + int output_bpp = pipe_config->dsc.compressed_bpp; > > + > > + if (output_bpp * adjusted_mode->crtc_clock >= > > + pipe_config->port_clock * 72) { > > + drm_dbg_kms(&dev_priv->drm, "UHBR check failed(required bw %d available %d)\n", > > + output_bpp * adjusted_mode->crtc_clock, pipe_config->port_clock * 72); > > + return -EINVAL; > > Doesn't this just mean the user can never enable this particular > mode? Would seem more sensible to account for the extra > limitation when we determine port_clock and/or compressed_bpp. So do you mean I should add this as part of the constraints, that we check, where we optimize port_clock? probably also then if we fail to find uncompressed more for that, then we need to try with DSC, also gradually decreasing compressed_bpp. Stan > > > + } > > + } > > + } > > > > ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state); > > if (ret) > > -- > > 2.37.3 > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 8b0e4defa3f1..36e368995bef 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -339,10 +339,20 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, conn_state, &limits, pipe_config->dp_m_n.tu, false); - } + if (ret < 0) + return ret; - if (ret) - return ret; + if (intel_dp_is_uhbr(pipe_config)) { + int output_bpp = pipe_config->dsc.compressed_bpp; + + if (output_bpp * adjusted_mode->crtc_clock >= + pipe_config->port_clock * 72) { + drm_dbg_kms(&dev_priv->drm, "UHBR check failed(required bw %d available %d)\n", + output_bpp * adjusted_mode->crtc_clock, pipe_config->port_clock * 72); + return -EINVAL; + } + } + } ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state); if (ret)
According to spec, we should check if output_bpp * pixel_rate is less than DDI clock * 72, if UHBR is used. HSDES: 1406899791 BSPEC: 49259 v2: - Removed wrong comment(Rodrigo Vivi) - Added HSDES to the commit msg(Rodrigo Vivi) - Moved UHBR check to the MST specific code v3: - Changed commit subject(Rodrigo Vivi) - Fixed the error message if check fails(Rodrigo Vivi) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-)