| Message ID | 20230118163040.29808-3-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Load LUTs with DSB | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Wednesday, January 18, 2023 10:00 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 02/13] drm/i915/dsb: Pimp debug/error prints > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Print the crtc/DSB id information to make it clear which DSB engine we're > talking about. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> LGTM. Reviewed-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c > b/drivers/gpu/drm/i915/display/intel_dsb.c > index 96bc117fd6a0..f41146fc84d7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -88,7 +88,8 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) > > /* each instruction is 2 dwords */ > return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2, > - "DSB buffer overflow\n"); > + "[CRTC:%d:%s] DSB %d buffer overflow\n", > + crtc->base.base.id, crtc->base.name, dsb->id); > } > > static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, @@ > -232,7 +233,8 @@ void intel_dsb_commit(struct intel_dsb *dsb) > return; > > if (is_dsb_busy(dev_priv, pipe, dsb->id)) { > - drm_err(&dev_priv->drm, "DSB engine is busy.\n"); > + drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n", > + crtc->base.base.id, crtc->base.name, dsb->id); > goto reset; > } > > @@ -250,7 +252,8 @@ void intel_dsb_commit(struct intel_dsb *dsb) > > if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) > drm_err(&dev_priv->drm, > - "Timed out waiting for DSB workload > completion.\n"); > + "[CRTC:%d:%s] DSB %d timed out waiting for idle\n", > + crtc->base.base.id, crtc->base.name, dsb->id); > > reset: > dsb->free_pos = 0; > @@ -325,7 +328,8 @@ struct intel_dsb *intel_dsb_prepare(struct intel_crtc > *crtc, > kfree(dsb); > out: > drm_info_once(&i915->drm, > - "DSB queue setup failed, will fallback to MMIO for display > HW programming\n"); > + "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to > MMIO for display HW programming\n", > + crtc->base.base.id, crtc->base.name, DSB1); > > return NULL; > } > -- > 2.38.2
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 96bc117fd6a0..f41146fc84d7 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -88,7 +88,8 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) /* each instruction is 2 dwords */ return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2, - "DSB buffer overflow\n"); + "[CRTC:%d:%s] DSB %d buffer overflow\n", + crtc->base.base.id, crtc->base.name, dsb->id); } static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, @@ -232,7 +233,8 @@ void intel_dsb_commit(struct intel_dsb *dsb) return; if (is_dsb_busy(dev_priv, pipe, dsb->id)) { - drm_err(&dev_priv->drm, "DSB engine is busy.\n"); + drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n", + crtc->base.base.id, crtc->base.name, dsb->id); goto reset; } @@ -250,7 +252,8 @@ void intel_dsb_commit(struct intel_dsb *dsb) if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) drm_err(&dev_priv->drm, - "Timed out waiting for DSB workload completion.\n"); + "[CRTC:%d:%s] DSB %d timed out waiting for idle\n", + crtc->base.base.id, crtc->base.name, dsb->id); reset: dsb->free_pos = 0; @@ -325,7 +328,8 @@ struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc, kfree(dsb); out: drm_info_once(&i915->drm, - "DSB queue setup failed, will fallback to MMIO for display HW programming\n"); + "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", + crtc->base.base.id, crtc->base.name, DSB1); return NULL; }