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[PATCHv2,1/2] drm: Add SDP Error Detection Configuration Register

Message ID 20230119114707.1425501-1-arun.r.murthy@intel.com (mailing list archive)
State New, archived
Headers show
Series [PATCHv2,1/2] drm: Add SDP Error Detection Configuration Register | expand

Commit Message

Arun R Murthy Jan. 19, 2023, 11:47 a.m. UTC
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.

v2: Update the macro name to reflect the DP spec(Harry)

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 include/drm/display/drm_dp.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Harry Wentland Jan. 19, 2023, 3:35 p.m. UTC | #1
On 1/19/23 06:47, Arun R Murthy wrote:
> DP2.0 E11 defines a new register to facilitate SDP error detection by a
> 128B/132B capable DPRX device.
> 
> v2: Update the macro name to reflect the DP spec(Harry)
> 
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  include/drm/display/drm_dp.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 632376c291db..358db4a9f167 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -692,6 +692,9 @@
>  # define DP_FEC_LANE_2_SELECT		    (2 << 4)
>  # define DP_FEC_LANE_3_SELECT		    (3 << 4)
>  
> +#define DP_SDP_ERROR_DETECTION_CONFIGURATION	0x121	/* DP 2.0 E11 */
> +#define DP_SDP_CRC16_128B132B_EN		BIT(0)
> +
>  #define DP_AUX_FRAME_SYNC_VALUE		    0x15c   /* eDP 1.4 */
>  # define DP_AUX_FRAME_SYNC_VALID	    (1 << 0)
>
diff mbox series

Patch

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..358db4a9f167 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -692,6 +692,9 @@ 
 # define DP_FEC_LANE_2_SELECT		    (2 << 4)
 # define DP_FEC_LANE_3_SELECT		    (3 << 4)
 
+#define DP_SDP_ERROR_DETECTION_CONFIGURATION	0x121	/* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN		BIT(0)
+
 #define DP_AUX_FRAME_SYNC_VALUE		    0x15c   /* eDP 1.4 */
 # define DP_AUX_FRAME_SYNC_VALID	    (1 << 0)