| Message ID | 20230123131611.2149-1-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Implement workaround for CDCLK PLL disable/enable | expand |
On Mon, Jan 23, 2023 at 03:16:11PM +0200, Stanislav Lisovskiy wrote: > It was reported that we might get a hung and loss of register access in > some cases when CDCLK PLL is disabled and then enabled, while squashing > is enabled. > As a workaround it was proposed by HW team that SW should disable squashing > when CDCLK PLL is being reenabled. What's the WA lineage for this WA? > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 0c107a38f9d0..e338f288c9ac 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1801,6 +1801,13 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > return true; > } > > +static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) > +{ > + return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) > + && dev_priv->display.cdclk.hw.vco > 0 > + && HAS_CDCLK_SQUASH(dev_priv)); > +} > + > static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > @@ -1815,9 +1822,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { > if (dev_priv->display.cdclk.hw.vco != vco) > adlp_cdclk_pll_crawl(dev_priv, vco); > - } else if (DISPLAY_VER(dev_priv) >= 11) > + } else if (DISPLAY_VER(dev_priv) >= 11) { > + if (pll_enable_wa_needed(dev_priv)) > + dg2_cdclk_squash_program(dev_priv, 0); > + > icl_cdclk_pll_update(dev_priv, vco); > - else > + } else > bxt_cdclk_pll_update(dev_priv, vco); > > waveform = cdclk_squash_waveform(dev_priv, cdclk); > -- > 2.37.3 >
On Mon, Jan 23, 2023 at 02:52:37PM -0500, Rodrigo Vivi wrote: > On Mon, Jan 23, 2023 at 03:16:11PM +0200, Stanislav Lisovskiy wrote: > > It was reported that we might get a hung and loss of register access in > > some cases when CDCLK PLL is disabled and then enabled, while squashing > > is enabled. > > As a workaround it was proposed by HW team that SW should disable squashing > > when CDCLK PLL is being reenabled. > > What's the WA lineage for this WA? Not sure, what you mean but HSD is: 14017300873 Stan > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++-- > > 1 file changed, 12 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index 0c107a38f9d0..e338f288c9ac 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -1801,6 +1801,13 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > > return true; > > } > > > > +static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) > > +{ > > + return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) > > + && dev_priv->display.cdclk.hw.vco > 0 > > + && HAS_CDCLK_SQUASH(dev_priv)); > > +} > > + > > static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > > const struct intel_cdclk_config *cdclk_config, > > enum pipe pipe) > > @@ -1815,9 +1822,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > > !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { > > if (dev_priv->display.cdclk.hw.vco != vco) > > adlp_cdclk_pll_crawl(dev_priv, vco); > > - } else if (DISPLAY_VER(dev_priv) >= 11) > > + } else if (DISPLAY_VER(dev_priv) >= 11) { > > + if (pll_enable_wa_needed(dev_priv)) > > + dg2_cdclk_squash_program(dev_priv, 0); > > + > > icl_cdclk_pll_update(dev_priv, vco); > > - else > > + } else > > bxt_cdclk_pll_update(dev_priv, vco); > > > > waveform = cdclk_squash_waveform(dev_priv, cdclk); > > -- > > 2.37.3 > >
On Tue, Jan 24, 2023 at 09:42:24AM +0200, Lisovskiy, Stanislav wrote: > On Mon, Jan 23, 2023 at 02:52:37PM -0500, Rodrigo Vivi wrote: > > On Mon, Jan 23, 2023 at 03:16:11PM +0200, Stanislav Lisovskiy wrote: > > > It was reported that we might get a hung and loss of register access in > > > some cases when CDCLK PLL is disabled and then enabled, while squashing > > > is enabled. > > > As a workaround it was proposed by HW team that SW should disable squashing > > > when CDCLK PLL is being reenabled. > > > > What's the WA lineage for this WA? > > Not sure, what you mean but HSD is: 14017300873 For this HSD, the wa lineage one is actually: Lineage: 15010685871 so you need to add the wa line for reference, something like: /* wa_15010685871: dg2, mtl */ but looking to the related ones there I don't believe it is yet confirmed to mtl... although it looks that there's a possibility of this staying for display_ver >= 13.... But more than that I'd like to get someone else from display team to run a deep review on this. Because I see that you are disabling it after the cdclk is locked up. > > Stan > > > > > > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++-- > > > 1 file changed, 12 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > index 0c107a38f9d0..e338f288c9ac 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > @@ -1801,6 +1801,13 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > > > return true; > > > } > > > > > > +static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) > > > +{ > > > + return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) > > > + && dev_priv->display.cdclk.hw.vco > 0 > > > + && HAS_CDCLK_SQUASH(dev_priv)); > > > +} > > > + > > > static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > > > const struct intel_cdclk_config *cdclk_config, > > > enum pipe pipe) > > > @@ -1815,9 +1822,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > > > !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { > > > if (dev_priv->display.cdclk.hw.vco != vco) > > > adlp_cdclk_pll_crawl(dev_priv, vco); > > > - } else if (DISPLAY_VER(dev_priv) >= 11) > > > + } else if (DISPLAY_VER(dev_priv) >= 11) { > > > + if (pll_enable_wa_needed(dev_priv)) > > > + dg2_cdclk_squash_program(dev_priv, 0); > > > + > > > icl_cdclk_pll_update(dev_priv, vco); > > > - else > > > + } else > > > bxt_cdclk_pll_update(dev_priv, vco); > > > > > > waveform = cdclk_squash_waveform(dev_priv, cdclk); > > > -- > > > 2.37.3 > > >
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 0c107a38f9d0..e338f288c9ac 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1801,6 +1801,13 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 return true; } +static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) +{ + return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) + && dev_priv->display.cdclk.hw.vco > 0 + && HAS_CDCLK_SQUASH(dev_priv)); +} + static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) @@ -1815,9 +1822,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { if (dev_priv->display.cdclk.hw.vco != vco) adlp_cdclk_pll_crawl(dev_priv, vco); - } else if (DISPLAY_VER(dev_priv) >= 11) + } else if (DISPLAY_VER(dev_priv) >= 11) { + if (pll_enable_wa_needed(dev_priv)) + dg2_cdclk_squash_program(dev_priv, 0); + icl_cdclk_pll_update(dev_priv, vco); - else + } else bxt_cdclk_pll_update(dev_priv, vco); waveform = cdclk_squash_waveform(dev_priv, cdclk);
It was reported that we might get a hung and loss of register access in some cases when CDCLK PLL is disabled and then enabled, while squashing is enabled. As a workaround it was proposed by HW team that SW should disable squashing when CDCLK PLL is being reenabled. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)