From patchwork Tue Jan 31 09:17:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janusz Krzysztofik X-Patchwork-Id: 13122581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FFE5C38142 for ; Tue, 31 Jan 2023 09:18:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6458C10E31A; Tue, 31 Jan 2023 09:18:00 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id B703E10E32B; Tue, 31 Jan 2023 09:17:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675156678; x=1706692678; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tzciVk8LP4p/TqsIOEeeJ/RvfEhNpsVE6QdphgFsalc=; b=a3diXOs9fxKOd+E6iqPVvfrnbI0d+WeIiNvtpUrL94iyRCa0UoVC35Oy Xn4+na9vfoxxYrikqvz28QcGrze8Rf8NDwTpRqXE/0Zjr+Cr73QBzrY1L ijwlIUU43Ltz//q5ZZcfMpDNMxqkdakIbmC2YtkFaNo5HMvo3DjbWfTbk Uzo0QByCkn0eJ7efbb6rVViVx6EyEm/4gmVbojs+sMGaYXfKcnAAwB1Ll plyRpTHhbe7hSPCkh4QqBsbzoKBKH6uj17N0oIDNHJDJc9wJd85cflH1o FgAQpxqYiPU1WbJK8hEbDJICi5c3Hg+6yPhkM2Y6gjlAjm/MZSBqIDjvD w==; X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="390154169" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="390154169" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 01:17:58 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="909837963" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="909837963" Received: from khernet-mobl.ger.corp.intel.com (HELO jkrzyszt-mobl1.ger.corp.intel.com) ([10.213.18.238]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2023 01:17:55 -0800 From: Janusz Krzysztofik To: Petri Latvala , Arkadiusz Hiler , Kamil Konieczny Date: Tue, 31 Jan 2023 10:17:31 +0100 Message-Id: <20230131091731.5892-3-janusz.krzysztofik@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230131091731.5892-1-janusz.krzysztofik@linux.intel.com> References: <20230131091731.5892-1-janusz.krzysztofik@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/perf: Exercise barrier race X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a new subtest focused on exercising interaction between perf open / close operations, which replace active barriers with perf requests, and concurrent barrier preallocate / acquire operations performed during context first pin / last unpin. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6333 Signed-off-by: Janusz Krzysztofik Cc: Chris Wilson --- tests/i915/perf.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/tests/i915/perf.c b/tests/i915/perf.c index e33cacc443..11a3ec21ab 100644 --- a/tests/i915/perf.c +++ b/tests/i915/perf.c @@ -39,6 +39,7 @@ #include #include "i915/gem.h" +#include "i915/gem_create.h" #include "i915/perf.h" #include "igt.h" #include "igt_perf.h" @@ -4885,7 +4886,27 @@ test_whitelisted_registers_userspace_config(void) i915_perf_remove_config(drm_fd, config_id); } -static void test_open_race(const struct intel_execution_engine2 *e, int timeout) +static void gem_exec_nop(int i915, const struct intel_execution_engine2 *e) +{ + const uint32_t bbe = MI_BATCH_BUFFER_END; + struct drm_i915_gem_exec_object2 obj = { }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + }; + + obj.handle = gem_create(i915, 4096); + gem_write(i915, obj.handle, 0, &bbe, sizeof(bbe)); + + execbuf.flags = e->flags; + gem_execbuf(i915, &execbuf); + + gem_sync(i915, obj.handle); + gem_close(i915, obj.handle); +} + +static void test_open_race(const struct intel_execution_engine2 *e, int timeout, + bool use_spin) { int *done; @@ -4926,6 +4947,12 @@ static void test_open_race(const struct intel_execution_engine2 *e, int timeout) ctx = gem_context_create_for_engine(i915, e->class, e->instance); gem_context_set_persistence(i915, ctx, persistence); + if (!use_spin) { + gem_exec_nop(i915, e); + gem_context_destroy(i915, ctx); + continue; + } + spin = __igt_spin_new(i915, ctx, .ahnd = ahnd); for (int i = random() % 7; i--; ) { if (random() & 1) { @@ -5330,7 +5357,17 @@ igt_main for_each_physical_engine(drm_fd, e) if (e->class == I915_ENGINE_CLASS_RENDER) igt_dynamic_f("%s", e->name) - test_open_race(e, 5); + test_open_race(e, 5, true); + } + + igt_describe("Exercise perf open/close against intensive barrier preallocate/acquire"); + igt_subtest_with_dynamic("barrier-race") { + const struct intel_execution_engine2 *e; + + for_each_physical_engine(drm_fd, e) + if (e->class == I915_ENGINE_CLASS_RENDER) + igt_dynamic_f("%s", e->name) + test_open_race(e, 5, false); } igt_fixture {