From patchwork Mon Feb 27 04:03:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13152722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7904C64ED6 for ; Mon, 27 Feb 2023 04:06:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 47E6910E195; Mon, 27 Feb 2023 04:06:24 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A20110E15C for ; Mon, 27 Feb 2023 04:06:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677470774; x=1709006774; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mQK5WA8u+J6KG6J0/VKTB7plwhLxEaDyhFn5JqY4V24=; b=MXrQhMWFYCt6ssBmo+2n8IDExMcM8ba18nyOfNjpQVCSTVmmNn45eGYd ZwCwJ4Re2Is0+XagXp/TynBNvMw2g4AXwKyVm2mUJSWK272w7U7w2Q1RL uNahXfmxqxm2k8YCl6VVnfcKD+v+Bg6sGXEtFUatdL6dpwHs7EdrIsT7v 3YxxFpApjpRUqMRbzhY5Uhq5T+0n3azNmWZMQqj6cNLAwPdz48ni9PMRm jWSLyRljSPddE87nJicHUVJttV8FFtvmVd0J2Unm0b20SegxDuMihaikN zmKrn5r+JOUQ1kZ7NWczWWPUWYLERpg6oZC6VKGgB1/6Cnj5EpTMB71Ih Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10633"; a="335251396" X-IronPort-AV: E=Sophos;i="5.97,330,1669104000"; d="scan'208";a="335251396" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2023 20:06:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10633"; a="783147021" X-IronPort-AV: E=Sophos;i="5.97,330,1669104000"; d="scan'208";a="783147021" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2023 20:06:12 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 27 Feb 2023 09:33:20 +0530 Message-Id: <20230227040324.130811-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227040324.130811-1-ankit.k.nautiyal@intel.com> References: <20230227040324.130811-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 09/13] drm/i915/display: Add helper function to check if sink_format is 420 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add an inline helper function to check if the sink_format is set to YCBCR420 format. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +++--- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1be15a1caa39..9bcccf02a2b1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -2067,4 +2067,10 @@ to_intel_frontbuffer(struct drm_framebuffer *fb) return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; } +static inline bool +intel_crtc_has_420_sink_format(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420; +} + #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 59919ad03a26..38ca6f676cb2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2188,7 +2188,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits, with_dsc); if (ret) { - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + if (intel_crtc_has_420_sink_format(crtc_state) || !connector->base.ycbcr_420_allowed || !drm_mode_is_420_also(info, adjusted_mode)) return ret; @@ -2903,7 +2903,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", str_enable_disable(intel_dp->has_hdmi_sink)); - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { + if (intel_crtc_has_420_sink_format(crtc_state)) { switch (crtc_state->output_format) { case INTEL_OUTPUT_FORMAT_YCBCR420: /* diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 15bf64a217c2..73e314f66367 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2048,7 +2048,7 @@ static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc return false; /* Display Wa_1405510057:icl,ehl */ - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 && + if (intel_crtc_has_420_sink_format(crtc_state) && bpc == 10 && DISPLAY_VER(dev_priv) == 11 && (adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start) % 8 == 2) @@ -2210,7 +2210,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector); ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); if (ret) { - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + if (intel_crtc_has_420_sink_format(crtc_state) || !connector->base.ycbcr_420_allowed || !drm_mode_is_420_also(info, adjusted_mode)) return ret; @@ -2295,7 +2295,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, return ret; } - if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { + if (intel_crtc_has_420_sink_format(pipe_config)) { ret = intel_panel_fitting(pipe_config, conn_state); if (ret) return ret;