From patchwork Mon Feb 27 04:03:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13152726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25E7CC7EE30 for ; Mon, 27 Feb 2023 04:06:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F55C10E353; Mon, 27 Feb 2023 04:06:27 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C7E610E195 for ; Mon, 27 Feb 2023 04:06:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677470779; x=1709006779; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MeVbIzLepY6Y65CgT7D6eMzP7DQE8ky69OefQUr+RLA=; b=jlh6SQluIJKwMkkFKux2Zu5Sn5hbFEkVShhYKgaINQhjJj1RIhmzsaJ3 YjMKLTSPNCUXuR5oboUDiq2xvOV5WU3/VrilbT7DQOBtzNawECsU5crPz uqG7Eyqz8bb0sszdOgQzj2cGLzFBAKq414CxKqGEGPXMVB9k3o/Pr6LFR toXy+yfsAAjPmT7n77mGSPBSmlgVu+pTiv0qplAHf/Vwj7pywKAlpajVx fKzEJqaMryIsnbFO/AbkwbX5xn/CpKqBAp+uQVpMvT8D3LNDN67GzqMxe TWzlHtZ2oZv+m9ZtE1Uz+qeWWeYanc7geyhWK2jJZPmpoc9cFbEAdSzB1 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10633"; a="335251409" X-IronPort-AV: E=Sophos;i="5.97,330,1669104000"; d="scan'208";a="335251409" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2023 20:06:19 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10633"; a="783147035" X-IronPort-AV: E=Sophos;i="5.97,330,1669104000"; d="scan'208";a="783147035" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2023 20:06:17 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 27 Feb 2023 09:33:23 +0530 Message-Id: <20230227040324.130811-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227040324.130811-1-ankit.k.nautiyal@intel.com> References: <20230227040324.130811-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 12/13] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During FRL bandwidth check for downstream HDMI2.1 sink, the min BPC supported is incorrectly taken for DP, and the check does not consider ybcr420 only modes. This patch fixes the bandwidth calculation similar to the TMDS case, by taking min 8Bpc and considering Ycbcr420 only modes. v2: Rebase Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++++++-------- 1 file changed, 45 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6f2f3e02c35f..18a0a258f49f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); static void intel_dp_unset_edid(struct intel_dp *intel_dp); +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -1029,6 +1030,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, return MODE_OK; } +static enum drm_mode_status +intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, + int bpc, enum intel_output_format sink_format) +{ + int target_bw; + int max_frl_bw; + int bpp = bpc * 3; + + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + target_clock /= 2; + + target_bw = bpp * target_clock; + + /* check for MAX FRL BW for both PCON and HDMI2.1 sink */ + max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw, + intel_dp_hdmi_sink_max_frl(intel_dp)); + + /* converting bw from Gbps to Kbps*/ + max_frl_bw = max_frl_bw * 1000000; + + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1037,24 +1064,30 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; - bool ycbcr_420_only; + bool ycbcr_420_only = drm_mode_is_420_only(info, mode); enum intel_output_format sink_format; + ycbcr_420_only = drm_mode_is_420_only(info, mode); + /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { - int target_bw; - int max_frl_bw; - int bpp = intel_dp_mode_min_output_bpp(connector, mode); - - target_bw = bpp * target_clock; - max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; - - /* converting bw from Gbps to Kbps*/ - max_frl_bw = max_frl_bw * 1000000; + if (ycbcr_420_only && connector->base.ycbcr_420_allowed) + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + else + sink_format = INTEL_OUTPUT_FORMAT_RGB; - if (target_bw > max_frl_bw) - return MODE_CLOCK_HIGH; + /* Assume 8bpc for the HDMI2.1 FRL BW check */ + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + if (status != MODE_OK) { + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + !drm_mode_is_420_also(info, mode)) + return status; + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + if (status != MODE_OK) + return status; + } return MODE_OK; } @@ -1063,13 +1096,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - ycbcr_420_only = drm_mode_is_420_only(info, mode); - - if (ycbcr_420_only && connector->base.ycbcr_420_allowed) - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - else - sink_format = INTEL_OUTPUT_FORMAT_RGB; - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true);